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Relocating Interrupt Vector Table

Japan Dave
Note: This was originally posted on 13th August 2010 at http://forums.arm.com

Hi,

               I want to know that whether it is possible to change the base address of vector table?... Working on this question, I got other few queries in my mind...

(1) Where is the base address for vector table is defined?? (CPU atleast needs that to add calculated offset according to type of interrupt / exception)

(2) Does different architectures / cores have different base addresses?

(3) The question it self on which I am working, how to change the base address of vector table?
  • Arm Employee Badge
    Note: This was originally posted on 17th August 2010 at http://forums.arm.com

    For Cortex-M3 and Cortex-M4, there is a Vector Table Offset Register to relocate vector table to CODE or SRAM memory.

    Some other microcontroller devices based on the Cortex-M0 (e.g. NXP LPC11xx) has a memory remap feature on its memory system (not a part of the processor) to allow vector table accesses to be optionally redirected to the SRAM.
  • Arm Employee Badge
    Note: This was originally posted on 13th August 2010 at http://forums.arm.com

    Which core(s) are you using?

    For most ARM cores (e.g. ARM9, ARM10...) the vector table can be located at either address 0x0 or 0xFFFF0000.  Which is used is controlled by a signal at Reset, and by the CP15 Control register after Reset.  Note - that it is virtual address 0x0 or 0xFFFF,0000.

    Cores that support TrustZone (e.g. ARM1176JZ(F)-S, Cortex-A{n}) can override the vector table location, and use any address.  Again controlled by CP15.  This can only be controlled after Reset, so for Reset itself you are still limited to the two locations.

    For Cortex-M cores, I believe there is similar support for relocating the vector table, but not really worked with them much.