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LDM for ARMv6 with RVDS 2.2.1

Naresh Sharma
Note: This was originally posted on 30th July 2010 at http://forums.arm.com

Hi All,

I'm trying to use LDM for ARMv6 with RVDS 2.2.1 (AXD 1.3.1 build 98) for unaligned memory access. Processor is ARM1136J-S for both build and AXD debug.

However, LDM results in data abort exception. LDR does not exhibit this error.

My questions are

1. Is it ARMv6 feature/ known-behaviour for LDM or is it RVDS 2.2.1/AXD 1.3.1 bug?
2. I see some usage of LDR/ LDM with dest register same as source register. I was wondering how ARM takes care to access the memory location from one register and then write data to the same register! I'm concerned with data-path to and fro the register.  Any insights?

Thank you for all help and guidance,

Naresh
Parents
  • Arm Employee Badge
    Note: This was originally posted on 30th July 2010 at http://forums.arm.com

    I had thought that AXD did not have ARM11 support, but its a long time since I last used it.  Anyway...

    If LDR works for the same address, than I would suspect address alignment.  The ARM11s (when correctly configured) support unaligned accesses - but only with certain instructions.  LDMs must always be word aligned, but not LDRs.  So that could be the problem.  If you look at the DFSR on entry to the abort it should confirm whether it is alignment or not.

    For 2, this is fine - as long as you do not specify the '!' which updates the address register.  So...

      LDM r1, {r0-r4)    would be ok
      LDM r1!, {r0-r4}   is not ok

    In the first case, the pipeline handles the updates in the correct order.
Reply
  • Arm Employee Badge
    Note: This was originally posted on 30th July 2010 at http://forums.arm.com

    I had thought that AXD did not have ARM11 support, but its a long time since I last used it.  Anyway...

    If LDR works for the same address, than I would suspect address alignment.  The ARM11s (when correctly configured) support unaligned accesses - but only with certain instructions.  LDMs must always be word aligned, but not LDRs.  So that could be the problem.  If you look at the DFSR on entry to the abort it should confirm whether it is alignment or not.

    For 2, this is fine - as long as you do not specify the '!' which updates the address register.  So...

      LDM r1, {r0-r4)    would be ok
      LDM r1!, {r0-r4}   is not ok

    In the first case, the pipeline handles the updates in the correct order.
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