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How JTAG take control of ARM core?

Ding Li
Note: This was originally posted on 29th July 2010 at http://forums.arm.com

Hello,

I have a question from customer regarding how to disable JTAG in their final product to prevent their application code from explosion from JTAG interface.

Since I am not familiar with JTAG debug module and ARM core interaction mechanism, I would like to know if there is any document talking about the JTAG debug detail procedure.

(1) We have a plan to disable the JTAG port during reset stage of the MCU, and enable it with the built-in ROM code in certain stage. I am not sure if it is workable, any attention needed?

(2) Is the system reset a must when entering JTAG debug mode? If not, please help explain the detail procedure on how JTAG take control of core.


Thanks a lot!
Parents
  • Note: This was originally posted on 5th August 2010 at http://forums.arm.com

    It depends on the chip you use. Some microcontrollers has firmware protection features (on the system level) so you will need to check with your microcontroller providers/vendors on this. It is unlikely that you can enable it by ROM code, but you might be able to erase the whole flash and reprogram it.


    Thanks, Joseph,

    I still woudl like to know what will happen if I disable JTAG ports in power on reset stage in SOC design level, which is done by setting the default / reset function of TDI/TDO pins as GPIO.

    Inside boot ROM code, I will enable the JTAG ports by software for certain conditions, for example flash content, or certain external pin status.

    In this way, I may take control of the JTAG access by software.  Will this solution work?

    Thanks a lot!
Reply
  • Note: This was originally posted on 5th August 2010 at http://forums.arm.com

    It depends on the chip you use. Some microcontrollers has firmware protection features (on the system level) so you will need to check with your microcontroller providers/vendors on this. It is unlikely that you can enable it by ROM code, but you might be able to erase the whole flash and reprogram it.


    Thanks, Joseph,

    I still woudl like to know what will happen if I disable JTAG ports in power on reset stage in SOC design level, which is done by setting the default / reset function of TDI/TDO pins as GPIO.

    Inside boot ROM code, I will enable the JTAG ports by software for certain conditions, for example flash content, or certain external pin status.

    In this way, I may take control of the JTAG access by software.  Will this solution work?

    Thanks a lot!
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