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Performance monitor event numbers in Tegra2 (Cortex-A9 MPCore)

Anthony Gutierrez
Note: This was originally posted on 16th July 2010 at http://forums.arm.com

I am trying to collect some data on a Tegra2 using the performance monitors. I have a question about some of the event numbers. I wanted to collect data on the number of instructions executed so I monitored event 0x08 since, according to the ARM Architecture Reference Manual ARMv7-A and ARMV7-R, this is supposed to be the number for the instruction count event. I wasn't getting anything other than 0. So, after looking around I found the Cortex-A9 Technical Reference Manual which states:

The Cortex-A9 processor implements the architectural events described in the ARM
Architecture Reference Manual, with the exception of:
0x08
Memory-reading instruction architecturally executed
0x0E
Procedure return, other than exception return, architecturally executed.


Which explains why I was getting 0 when monitoring event 0x08. But this states that this event is for mem reads. So which document is correct? If 0x08 is for mem reads, which event monitors instruction count? According to the architecture reference manual 0x06 is for mem reads.

thanks,

Tony
  • Note: This was originally posted on 19th July 2010 at http://forums.arm.com

    I'm pretty sure that event 0x08 is the instruction counter. So, if this event is not implemented does anybody know how I can get a reasonably accurate instruction count?
  • Note: This was originally posted on 20th July 2010 at http://forums.arm.com

    The implementation-specific event 0x68 (Instructions coming out of the core renaming stage) is probably the closest that you are going to get on Cortex-A9 I think. This counts all instructions as they are queued in the out-of-order pipeline, so will count instructions which are speculatively issued and then thrown away because of a branch or an exception. It is therefore going to give a high count, but it will be an upper bound at least ...


    I was thinking of using 0x68 to get speculative instructions then subtract off the counters for branch mispredicts, exceptions, and cache miss stalls. Would this be a decent approximation to the actual instruction count?

    Also is event 0x01, icache misses implemented? The reference manual says it is but, I can never get anything other than 0.

    thanks,

    Tony
  • Arm Employee Badge
    Note: This was originally posted on 20th July 2010 at http://forums.arm.com

    I'm pretty sure that event 0x08 is the instruction counter. So, if this event is not implemented does anybody know how I can get a reasonably accurate instruction count?


    The implementation-specific event 0x68 (Instructions coming out of the core renaming stage) is probably the closest that you are going to get on Cortex-A9 I think. This counts all instructions as they are queued in the out-of-order pipeline, so will count instructions which are speculatively issued and then thrown away because of a branch or an exception. It is therefore going to give a high count, but it will be an upper bound at least ...