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Unable to clear BFSR

Note: This was originally posted on 20th July 2010 at http://forums.arm.com

Hi ,

I have situation where I get ERROR(0x1) on HRESP of SAHB bus , which is as expected.
I have my Bus fault handler enabled and it is being serviced. I can read the BFSR (Bus Fault Status Register)
and can see corresponding transactions on PPB bus

@ Nth cycle

HADDRppb   = 0xE000ED29 ( address of BFSR )
HTRANSppb = 0x2 (NON SEQ)
HSIZEppb     = 0x0 ( 8 bits transfer )
HRESPppb   = 0x0
HWRITEppb = 0x0 ( Read operation of BFSR )

@N+1 cycle
HRDATAppb = 0x8200

Now for clearing the BFSR , I intend to write 0xff.
However, I see following transactions on PPB bus

@ Mth cycle

HADDRppb   = 0xE000ED29 ( address of BFSR )
HTRANSppb = 0x2 (NON SEQ)
HSIZEppb     = 0x0 ( 8 bits transfer )
HRESPppb   = 0x0
HWRITEppb = 0x1 (Write operation of BFSR )

@M+1 th cycle
HWDATAppb = 0xffffffff

As per AHB protocol, HWDATAppb should have 0xffff_ffff in the Mth cycle itself
Can anyone help me out as why write data is coming one cycle delayed ?
As a result I am unable clear the Bus Fault Status Register( BFSR).

Thanks,
Vinayak

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Vinayak Ray over 12 years ago

Note: This was originally posted on 20th July 2010 at http://forums.arm.com

In AHB, HWDATA and HRDATA both occur in cycles after the HADDR, HTRANS, HSIZE etc are presented.

hth
s.

My bus fault handler was being called repeatedly , which gave the false impression of BFSR not being cleared.
Thanks....
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Vinayak Ray over 12 years ago

Note: This was originally posted on 20th July 2010 at http://forums.arm.com

In AHB, HWDATA and HRDATA both occur in cycles after the HADDR, HTRANS, HSIZE etc are presented.

hth
s.

My bus fault handler was being called repeatedly , which gave the false impression of BFSR not being cleared.
Thanks....
Cancel
Vote up 0 Vote down

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