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Interrupt priority levels:

David Clark
Note: This was originally posted on 16th June 2010 at http://forums.arm.com

I feel this is probably documented somewhere, but I'm failing to find it, so here goes.

Let's say I have 2 interrupts/exceptions at the same priority level, and let's say they're both masked (due to PRIMASK, due to BASEPRI, etc...)

Let's say they both become pended, but they don't fire, because they're masked.

Now let's say the interrupts are unmasked simultaneously.  What determines which interrupt will fire first?

  • Is there a table with a "pecking order" somewhere in the ARM documentation?
  • Does it depend on which arrived first?  (Very unlikely)
  • Is it random / undefined?  (Also extremely unlikely)

Just wondering how to understand what will happen in such a scenario.


As a more concrete example, I'm sitting here looking at a table showing the SVC exception at slot 11, and the PendSV exception at the "lower" slot 14; let's say:


  • they're both configured to be a certain level, the same level (let's say 0x80)
  • BASEPRI is now set to 0x40
  • Both PendSV and SVC become pending
  • BASEPRI is adjused back to 0

Is it clear in this scenario which exception handler will run first?

Thank you.