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NVIC first cycle operation

Chintan Dave
Note: This was originally posted on 10th May 2010 at http://forums.arm.com

Hi,
   I have read the Arm_cortexm3_r1p1_trm.pdf for NVIC understanding. In that one sentence is given on page 5-13 "The NVIC indicates to the processor core, in the cycle after INTISR[2] was received,that an interrupt has been received, and the processor initiates the stack push and vector fetch in the following cycle." What is the reason to start the operation in the next cycle, not in the same cycle?
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  • Note: This was originally posted on 12th May 2010 at http://forums.arm.com

    Because that's how the logic works ... =)

    Because logic works on register slices which are latched on clock edges ... the CPU cannot start working on calculating an NVI address until it has been told that an NVI has been received by the NVIC, which is in the previous logic slice, so there is one cycle delay ...


    Hi,
       Thats right but if u see in the waveform when the interrupt is detected in NVIC, the process of stacking will start after next to next clock cycle. Actually it will inform the CPU in next cycle(2nd cycle) and process of stacking will starting in next cycle(3rd cycle). Why the stacking will not be start in 2nd cycle while CPU is detecting the interrupt?
Reply
  • Note: This was originally posted on 12th May 2010 at http://forums.arm.com

    Because that's how the logic works ... =)

    Because logic works on register slices which are latched on clock edges ... the CPU cannot start working on calculating an NVI address until it has been told that an NVI has been received by the NVIC, which is in the previous logic slice, so there is one cycle delay ...


    Hi,
       Thats right but if u see in the waveform when the interrupt is detected in NVIC, the process of stacking will start after next to next clock cycle. Actually it will inform the CPU in next cycle(2nd cycle) and process of stacking will starting in next cycle(3rd cycle). Why the stacking will not be start in 2nd cycle while CPU is detecting the interrupt?
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