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swdp opearation in cortex-M3 /cortex-M0

devendra reddy
Note: This was originally posted on 21st April 2010 at http://forums.arm.com

we are working on a project to implement swjtag debugger for cortex boards. we had the reference manuals for cortex swdp, core sight, etc  available at infocenter.arm.com

we are trying it  accordingly. we were able to generate the switching sequences, packets etc properly as per the information we have but we couldn't get any acknowledgment packets from the processor. we are sure that we are missing some timing/other details . we will be thankful if you can help us in getting the complete timing sequence from power-on of the processor to ID code read in SWDP mode.that means to change the processor mode to swdp mode and requesting ID CODE read..

we are using our own compiled version of openocd software as debug software, we are generated the sequences using this software and verified this  sequence from FT2232H to cortex processor using logic analyzer. We are generating the sequences perfectly as given in the reference manual of cortex.
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  • Note: This was originally posted on 6th March 2011 at http://forums.arm.com

    Hello!

    I am creating Open Source SWD library http://libswd.sf.net that will be incorporated into UrJTAG and OpenOCD.. and had exactly the same issue that comes from incompetent messy documentation (nightmare!!) provided by ARM.

    1. IDCODE register is on DP, therefore APnDP should be 0, not 1 as stated in documentation.
    2. After RESET, JTAG-TO-SWD, RESET you need additional IDLE sequence (SWDIOTMS=0 + 8 pulses on SWCLK) before REQUEST, otherwise target won't respond. There is no even half word on this in the jtag-to-swd section of the documentation!
    3. Remember that ACK and DATA are clocked out LSBfirst not MSBfirst as displayed on the documentation, which is confusing.

    I got this working using FT2232H chip working with highest possible speed :-)

    Best regads,
    Tomek Cedro
Reply
  • Note: This was originally posted on 6th March 2011 at http://forums.arm.com

    Hello!

    I am creating Open Source SWD library http://libswd.sf.net that will be incorporated into UrJTAG and OpenOCD.. and had exactly the same issue that comes from incompetent messy documentation (nightmare!!) provided by ARM.

    1. IDCODE register is on DP, therefore APnDP should be 0, not 1 as stated in documentation.
    2. After RESET, JTAG-TO-SWD, RESET you need additional IDLE sequence (SWDIOTMS=0 + 8 pulses on SWCLK) before REQUEST, otherwise target won't respond. There is no even half word on this in the jtag-to-swd section of the documentation!
    3. Remember that ACK and DATA are clocked out LSBfirst not MSBfirst as displayed on the documentation, which is confusing.

    I got this working using FT2232H chip working with highest possible speed :-)

    Best regads,
    Tomek Cedro
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