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swdp opearation in cortex-M3 /cortex-M0

Note: This was originally posted on 21st April 2010 at http://forums.arm.com

we are working on a project to implement swjtag debugger for cortex boards. we had the reference manuals for cortex swdp, core sight, etc  available at infocenter.arm.com

we are trying it  accordingly. we were able to generate the switching sequences, packets etc properly as per the information we have but we couldn't get any acknowledgment packets from the processor. we are sure that we are missing some timing/other details . we will be thankful if you can help us in getting the complete timing sequence from power-on of the processor to ID code read in SWDP mode.that means to change the processor mode to swdp mode and requesting ID CODE read..

we are using our own compiled version of openocd software as debug software, we are generated the sequences using this software and verified this  sequence from FT2232H to cortex processor using logic analyzer. We are generating the sequences perfectly as given in the reference manual of cortex.
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  • Note: This was originally posted on 22nd April 2010 at http://forums.arm.com

    thanks for your reply Joseph..

    We have used cortex-M3 from Luminary Micro(LM3S6965), We sent the sequences given in the Core-sight trm ,

    The sequence order we sent to the processor:

    1. 56 number of 1's on SWDIOTMS.(i.e more than 50 clk cycles)
    2. The 16 bit sequence given by the ARM trm
    3. 56 number of 1's on SWDIOTMS.

    with this we can assume it changed to SWD mode

    we sent the data to perform IDCODE register read..  that sequences are

    1. one time we have sent 0 to indicate the start of the packet request ( because the start bit ='1')/ one time we directly sent the ID CODE register read  request


    2. the command for this operation :  1 1 1 0 0 0 0 1 

      start=1, (1 bit MSB)
      ID CODE register is AP APnDP bit =1(2nd bit)
      RnW bit=1 for read operation(3rd bit)
    A[2:3]=00 for ID CODE(4,5 bits)
    Parity bit=0 (6th bit)
    stop bit=0 (7th bit)
    park bit= 1 (8th bit)

    by sending this command sequence , after 1 Trn clock cycle I tried to  read the acknowledge ( the data from the processor i .e next 3 bits..) i got all 1's..

    this is not in the possible acknowledgment..

    Can anybody help with this issue..??
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  • Note: This was originally posted on 22nd April 2010 at http://forums.arm.com

    thanks for your reply Joseph..

    We have used cortex-M3 from Luminary Micro(LM3S6965), We sent the sequences given in the Core-sight trm ,

    The sequence order we sent to the processor:

    1. 56 number of 1's on SWDIOTMS.(i.e more than 50 clk cycles)
    2. The 16 bit sequence given by the ARM trm
    3. 56 number of 1's on SWDIOTMS.

    with this we can assume it changed to SWD mode

    we sent the data to perform IDCODE register read..  that sequences are

    1. one time we have sent 0 to indicate the start of the packet request ( because the start bit ='1')/ one time we directly sent the ID CODE register read  request


    2. the command for this operation :  1 1 1 0 0 0 0 1 

      start=1, (1 bit MSB)
      ID CODE register is AP APnDP bit =1(2nd bit)
      RnW bit=1 for read operation(3rd bit)
    A[2:3]=00 for ID CODE(4,5 bits)
    Parity bit=0 (6th bit)
    stop bit=0 (7th bit)
    park bit= 1 (8th bit)

    by sending this command sequence , after 1 Trn clock cycle I tried to  read the acknowledge ( the data from the processor i .e next 3 bits..) i got all 1's..

    this is not in the possible acknowledgment..

    Can anybody help with this issue..??
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