Arm Community
Site
Search
User
Site
Search
User
Support forums
Arm Development Studio forum
HELP ! ARM 926 ejs icache and dcache
Jump...
Cancel
Locked
Locked
Replies
3 replies
Subscribers
119 subscribers
Views
2845 views
Users
0 members are here
Options
Share
More actions
Cancel
Related
How was your experience today?
This discussion has been locked.
You can no longer post new replies to this discussion. If you have a question you can start a new discussion
HELP ! ARM 926 ejs icache and dcache
Matt Luo
over 12 years ago
Note: This was originally posted on 11th February 2010 at
http://forums.arm.com
The system memory is SDRAM, and NAND booting. MMU enable, allocate low address space for code and read-only data. Hight address space for read-write data. They are all cacheable and bufferable. Code running in the low address space(read only segment) is better than running in the high address space(read-write segment). So , I doubt whether the icache is enable for the hight address space(read-write segment). But, in the datasheet ,there is no description about the icache influence space.
Parents
mark nicholson
over 12 years ago
Note: This was originally posted on 11th February 2010 at
http://forums.arm.com
The page table entries control which areas (of the whole 32bit address space) are cacheable. This is usually defined in 1MB blocks. (but can be defined in 4KB blocks in some areas). Are you 100% sure the cacheable attributes are the same for the lower and higher areas of memory you mention?
Cancel
Vote up
0
Vote down
Cancel
Reply
mark nicholson
over 12 years ago
Note: This was originally posted on 11th February 2010 at
http://forums.arm.com
The page table entries control which areas (of the whole 32bit address space) are cacheable. This is usually defined in 1MB blocks. (but can be defined in 4KB blocks in some areas). Are you 100% sure the cacheable attributes are the same for the lower and higher areas of memory you mention?
Cancel
Vote up
0
Vote down
Cancel
Children
No data