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HELP ! ARM 926 ejs icache and dcache

Matt Luo
Note: This was originally posted on 11th February 2010 at http://forums.arm.com

The system memory is SDRAM, and NAND booting. MMU enable, allocate low address space for code and read-only data. Hight address space for read-write data. They are all cacheable and bufferable. Code running in the low address space(read only segment) is better than running in the high address space(read-write segment). So , I doubt whether the icache is enable for the hight address space(read-write segment). But, in the datasheet ,there is no description about the icache influence space.
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  • Note: This was originally posted on 11th February 2010 at http://forums.arm.com

    The page table entries control which areas (of the whole 32bit address space) are cacheable. This is usually defined in 1MB blocks. (but can be defined in 4KB blocks in some areas). Are you 100% sure the cacheable attributes are the same for the lower and higher areas of memory you mention?
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  • Note: This was originally posted on 11th February 2010 at http://forums.arm.com

    The page table entries control which areas (of the whole 32bit address space) are cacheable. This is usually defined in 1MB blocks. (but can be defined in 4KB blocks in some areas). Are you 100% sure the cacheable attributes are the same for the lower and higher areas of memory you mention?
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