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HELP ! ARM 926 ejs icache and dcache

Matt Luo
Note: This was originally posted on 11th February 2010 at http://forums.arm.com

The system memory is SDRAM, and NAND booting. MMU enable, allocate low address space for code and read-only data. Hight address space for read-write data. They are all cacheable and bufferable. Code running in the low address space(read only segment) is better than running in the high address space(read-write segment). So , I doubt whether the icache is enable for the hight address space(read-write segment). But, in the datasheet ,there is no description about the icache influence space.
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  • Note: This was originally posted on 11th February 2010 at http://forums.arm.com

    Then (unless I'm missing something) code running from either area should use the cache.

    Unless of course (for whatever) reason the cache is beign deliberately disabled in one area of your codebase (by writing to CP15 control).

    If you have a ARM11 or Cortex device - you could consider using the PMU to measure cache hits when executing code from the different areas.
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  • Note: This was originally posted on 11th February 2010 at http://forums.arm.com

    Then (unless I'm missing something) code running from either area should use the cache.

    Unless of course (for whatever) reason the cache is beign deliberately disabled in one area of your codebase (by writing to CP15 control).

    If you have a ARM11 or Cortex device - you could consider using the PMU to measure cache hits when executing code from the different areas.
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