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HELP ! ARM 926 ejs icache and dcache

Note: This was originally posted on 11th February 2010 at http://forums.arm.com

The system memory is SDRAM, and NAND booting. MMU enable, allocate low address space for code and read-only data. Hight address space for read-write data. They are all cacheable and bufferable. Code running in the low address space(read only segment) is better than running in the high address space(read-write segment). So , I doubt whether the icache is enable for the hight address space(read-write segment). But, in the datasheet ,there is no description about the icache influence space.

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Matt Luo over 12 years ago

Note: This was originally posted on 11th February 2010 at http://forums.arm.com

Yes, I am sure. And I have wrote and read the page table entry. The lower address memory is tiny page, and the higher address memory is coarse page. Both are cacheable and bufferable.
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Matt Luo over 12 years ago

Note: This was originally posted on 11th February 2010 at http://forums.arm.com

Yes, I am sure. And I have wrote and read the page table entry. The lower address memory is tiny page, and the higher address memory is coarse page. Both are cacheable and bufferable.
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HELP &#33; ARM 926 ejs icache and dcache

HELP ! ARM 926 ejs icache and dcache