• Locked Locked
  • Replies 5 replies
  • Subscribers 119 subscribers
  • Views 4370 views
  • Users 0 members are here
2025 survey

We are running a survey to help us improve the experience for all of our members. If you see the survey appear, please take the time to tell us about your experience if you can.

Options
Related
How was your experience today?
This discussion has been locked.
You can no longer post new replies to this discussion. If you have a question you can start a new discussion

Performance Monitoring features for Cortex A8

Smitha Joseph
Note: This was originally posted on 22nd January 2010 at http://forums.arm.com

Hi,

I am trying to use the performance counter feature in Cortex A8. I have downloaded the sample code given here : [url="http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.faqs/ka4237.html"]http://infocenter.arm.com/help/index.jsp?t...aqs/ka4237.html[/url]

I am able to find the cycles taken via the cycle counter. But when I set an event to count, the counter always printing zero. The register contents when viewed in RV Debugger shows the contents to be untouched(all excalamation marks!!)..even the cycle counter is not showing its contents.

It would be of great help if you could give some pointers regarding what to check for/what I might be missing out?

Thanks,
Smitha Joseph
  • Note: This was originally posted on 22nd January 2010 at http://forums.arm.com

    Hi Raghavendra,

    Thanks for your reply. I have been able to set the User Enable Register to 1 using the instruction given in TRM. But still the event counter is giving 0. From the link that I had given in my previous post, I got the impression that the performance counters works on Simulator.

    Has anyone been able to access performance event counters on Simulator?

    Thanks,
    Smitha Joseph
  • Note: This was originally posted on 22nd January 2010 at http://forums.arm.com

    Hi Smitha,
       
            I also observed the same problem with CortexA8 in RVDS(3.3Version). My observations regarding this issue is - The porformance coprocessor register must be enabled. But when I m trying to do that in debugger it is not getting enabled. I think the code which you downloaded works on the board not on the simulator.

    Thanks & Regards,
    M. Raghavendra Prasad.
  • Arm Employee Badge
    Note: This was originally posted on 20th September 2011 at http://forums.arm.com


    Has anyone been able to access performance event counters on Simulator?


    I am afraid the simulator is the cause of the problem.  The models provided by ARM only model the CCNT.  The registers for the configurable counters are present, but don;t do anything.
  • Note: This was originally posted on 5th December 2012 at http://forums.arm.com



    Has anyone been able to access performance event counters on Simulator?


    I am afraid the simulator is the cause of the problem.  The models provided by ARM only model the CCNT.  The registers for the configurable counters are present, but don;t do anything.


    I have been trying to use PMU with Cortex-A9 and the results are same i.e. unable to count the events occurred other than the cycle count.


    The surprising thing is that if I set event 0x11 (cycle count) with the above set of PMU registers, I am able to find the cycles taken through PMXEVCNTR (Event Count Register) which
    matches with the value of PMCCNTR (Cycle count register). All other events won't bring any value other than zero in counters. This confirms that the set of other co-processor registers such as PMCNTENSET, PMCNTENCLR, PMSELR, PMXEVTYPER, PMXENCNTR etc are also working from its model as I followed the following sequence to perform cycle counts.
    • Disable performance counters
    • Set what each event counter will count
    • Set cycle counter tick rate
    • Reset performance counters
    • Enable performance counters
    • Call function to profile
    • Disable performance counters
    • Read out performance counters
    • Check that performance counters did not overflow
  • Note: This was originally posted on 19th September 2011 at http://forums.arm.com

    Hi Smitha,


    I am experiencing the same problems as you - the cycle counter works, but not the performance counters (always 0). I have tested this by running the necessary code in the kernel, i.e., in privileged mode, as a kernel module.

    What I have found is that the DBGEN signal needs to be raised for the counters to work as well as the cycle counter, but I do not know how to raise this line from software. Do you think this could be the problem? Have you found out what was your problem?

    Any solutions you may have found to this problem would be greatly appreciated!


    Stein