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Data abort

mcarthy mcarthy
Note: This was originally posted on 30th January 2010 at http://forums.arm.com

Hi ,
  I am working on arm from past few momths.I have one question that in ARM why unalligned address operation will give data abort ?and  is this thing will be happened for any special case ?Pleae help me to know actually when and why it will be happened. I came across thorugh some sites but still not get a clear picture.

Second thing if a value is not found then MMU misses the caches but how will i know the misses happened.?


I am looking forward to you .

Thanks
Mac
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  • Note: This was originally posted on 31st January 2010 at http://forums.arm.com

    Since ARMv6 (ARM11) unaligned transactions are support if the CPU is configured correctly, at least for non-multiple load/stores.

    Unaligned transactions are naturally hard for the hardware, as they potentially require a single word/half-word load/store being converted into multiple bus transactions



    I'm not sure what the question here is.

    hth
    s.

    hi,

    Thanks for the reply .Can you please say little bit more on this that  why unalligned adress operation will give us data abort .? Is it always to do the same ?
    The second question is :-When an instruction requests data from a cache, if the data is not there, a cache "˜miss' results,so will i know that "miss" happen..... means how to check that ?

    Thanks

    Macy
Reply
  • Note: This was originally posted on 31st January 2010 at http://forums.arm.com

    Since ARMv6 (ARM11) unaligned transactions are support if the CPU is configured correctly, at least for non-multiple load/stores.

    Unaligned transactions are naturally hard for the hardware, as they potentially require a single word/half-word load/store being converted into multiple bus transactions



    I'm not sure what the question here is.

    hth
    s.

    hi,

    Thanks for the reply .Can you please say little bit more on this that  why unalligned adress operation will give us data abort .? Is it always to do the same ?
    The second question is :-When an instruction requests data from a cache, if the data is not there, a cache "˜miss' results,so will i know that "miss" happen..... means how to check that ?

    Thanks

    Macy
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