The destination register is in the instruction encoding, and order constraints of a sequence of instructions will be enforced at the logical issue stage (although what this means in terms of when a register file is actually updated in a real implementation varies). This is really "micro architecture" - i.e. something which is decided by a specific implementation., and which is purposefully hidden from the programmer because it changes for different power or performance targets needed for a particular processor design. Even actually defining what a register file is an interesting problem ... there are likely to be multiple versions of the same register in existence at the same time, representing different temporal states - either in a physical register file or in different stages in the execution pipeline or forwarding paths. There may be the logical concept of a "register bank unit", but in high performance implementations reality is rarely that simple.Why do you need to know?Iso