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Which unit gives destination register number which is updating by execution unit

Note: This was originally posted on 4th January 2010 at http://forums.arm.com

Hi,
If i want to update my destination register,i have to pass register number and data value which is updating that register.which unit will give the register number to register bank unit? Is it execution unit or decoder unit? If answer is execution unit then why?

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Peter Harris over 12 years ago

Note: This was originally posted on 5th January 2010 at http://forums.arm.com

The destination register is in the instruction encoding, and order constraints of a sequence of instructions will be enforced at the logical issue stage (although what this means in terms of when a register file is actually updated in a real implementation varies).

This is really "micro architecture" - i.e. something which is decided by a specific implementation., and which is purposefully hidden from the programmer because it changes for different power or performance targets needed for a particular processor design. Even actually defining what a register file is an interesting problem ... there are likely to be multiple versions of the same register in existence at the same time, representing different temporal states - either in a physical register file or in different stages in the execution pipeline or forwarding paths. There may be the logical concept of a "register bank unit", but in high performance implementations reality is rarely that simple.

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Peter Harris over 12 years ago

Note: This was originally posted on 5th January 2010 at http://forums.arm.com

The destination register is in the instruction encoding, and order constraints of a sequence of instructions will be enforced at the logical issue stage (although what this means in terms of when a register file is actually updated in a real implementation varies).

This is really "micro architecture" - i.e. something which is decided by a specific implementation., and which is purposefully hidden from the programmer because it changes for different power or performance targets needed for a particular processor design. Even actually defining what a register file is an interesting problem ... there are likely to be multiple versions of the same register in existence at the same time, representing different temporal states - either in a physical register file or in different stages in the execution pipeline or forwarding paths. There may be the logical concept of a "register bank unit", but in high performance implementations reality is rarely that simple.

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Iso
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