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Basic AHB doubts....need help

kireeti kireeti
Note: This was originally posted on 26th November 2009 at http://forums.arm.com

Hello All,
i have been going through AHB spec from two weeks and i am stuck (a little confused)with some basic issues.

1)Is the address in burst is incremented by Master logic of AHB or is it from Processor (Main Master)

2)Page 3-5 Paragraph4 "The address cannot be extended and therefore all slaves must sample the address during this time. The data, however, can be extended using the HREADY signal. When LOW this signal causes wait states to be inserted into the transfer and allows extra time for the slave to provide or sample data."  But any figure i see with Data phase extended with the help of HREADY there is also Address phase of the next transfer extended.My understanding is that Processor (Main Master) which is connected to AHB Master gives Address once but AHB Master extends the address phase and doesn't take another address from Processor (Main Master).Is this right or is it something that i am missing.

3)Example : @ fourth posedge clock the MASTER sees HREADY as high and HRESP as OKAY and keeps the address and control signals in the same clock.Now this HREADY and HRESP denotes the condition for the previous transfer ?

4)What is the main function of HSEL.There is not much given about it in the Spec.


Thanks
Parents
  • Note: This was originally posted on 27th November 2009 at http://forums.arm.com

    Thanks Sim,

    But
    1)I couldn't get it right.An example to take in a burst of INCR4 and Halfword the Master gives address of 34.Is it the responsibility of Master logic or Slave logic to increment the address. (34-36-38-3A)
    3)can you please elaborate this (HREADY + HRESP correspond to the HADDR when HREADY was last high) with a figure explanation from the spec.

    thanks
Reply
  • Note: This was originally posted on 27th November 2009 at http://forums.arm.com

    Thanks Sim,

    But
    1)I couldn't get it right.An example to take in a burst of INCR4 and Halfword the Master gives address of 34.Is it the responsibility of Master logic or Slave logic to increment the address. (34-36-38-3A)
    3)can you please elaborate this (HREADY + HRESP correspond to the HADDR when HREADY was last high) with a figure explanation from the spec.

    thanks
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