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Profiling on Cortex A9 RTSM with cache enabled

Naveen G
Note: This was originally posted on 19th November 2009 at http://forums.arm.com

I am new to RVDS tools. I profiled my code on realview profiler. How reliable are these figures. Does these figures consider I-Cache and D-Cache effects. Is the cache enabled by default in RTSM or do I need to enable.
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  • Arm Employee Badge
    Note: This was originally posted on 20th November 2009 at http://forums.arm.com

    I'm not aware of any cycle-accurate or even cycle-approximate system models for a Cortex-A9 (could be wrong).

    Real hardware really is the best option if you want accuracy for high speed application cores - system behaviors such as L1 cache sizes, L2 size and latency, and L3 bus bandwidth / latency are really all critical to the performance of software running on a modern processor, and are all things which models tend to ignore.
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  • Arm Employee Badge
    Note: This was originally posted on 20th November 2009 at http://forums.arm.com

    I'm not aware of any cycle-accurate or even cycle-approximate system models for a Cortex-A9 (could be wrong).

    Real hardware really is the best option if you want accuracy for high speed application cores - system behaviors such as L1 cache sizes, L2 size and latency, and L3 bus bandwidth / latency are really all critical to the performance of software running on a modern processor, and are all things which models tend to ignore.
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