Arm Development Studio forum Cortex A9 FIQ and IRQ interrupts

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Cortex A9 FIQ and IRQ interrupts

Eugen Mandrenko over 12 years ago

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Peter Harris over 12 years ago

Note: This was originally posted on 13th November 2009 at http://forums.arm.com

By non-secure interrupts I assume you mean configured as non-secure in the GIC configuration.

How is the CP15 Secure Configuration Register configured to route interrupts - if CP15 is configured to route interrupts to the "Non-secure" world, then you will have to have set up an appropriate piece of monitor mode code to perform the world switch (so control can be passed to the non-secure interrupt handler). That said - a non-secure GIC interrupt can still be routed to the secure world in the CPU - the CPU and the GIC are programmed separately.

There is a good guide to TrustZone interrupt handling in the ARM document library:

[url="http://infocenter.arm.com/help/topic/com.arm.doc.prd29-genc-009492c/index.html"]http://infocenter.arm.com/help/topic/com.a...492c/index.html[/url]
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Peter Harris over 12 years ago

Note: This was originally posted on 13th November 2009 at http://forums.arm.com

By non-secure interrupts I assume you mean configured as non-secure in the GIC configuration.

How is the CP15 Secure Configuration Register configured to route interrupts - if CP15 is configured to route interrupts to the "Non-secure" world, then you will have to have set up an appropriate piece of monitor mode code to perform the world switch (so control can be passed to the non-secure interrupt handler). That said - a non-secure GIC interrupt can still be routed to the secure world in the CPU - the CPU and the GIC are programmed separately.

There is a good guide to TrustZone interrupt handling in the ARM document library:

[url="http://infocenter.arm.com/help/topic/com.arm.doc.prd29-genc-009492c/index.html"]http://infocenter.arm.com/help/topic/com.a...492c/index.html[/url]
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