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Cortex A9 FIQ and IRQ interrupts

Eugen Mandrenko
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    Note: This was originally posted on 18th November 2009 at http://forums.arm.com

    I am using GIC in Cortex A9MP and want to use both IRQ and FIQ handler for diferent interrupts. To select the handler I am going to set corresponding bits in Interrupt Security Registers (ICDISR), but I am going to use only secure world. Will it work?
    I expect to catch non-secure interrupt by interrupt handler in secure world, but I can't do it. I see that Highest Pending Interrupt Register (ICCHPIR) doesn't get ID of non-secure interrupt, despite non-secure interrupts are enabled in CPU Interface Control Register (ICCICR) and interrupt has pending status in the distributor.  Has anybody done something similar?
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    Note: This was originally posted on 18th November 2009 at http://forums.arm.com

    I am using GIC in Cortex A9MP and want to use both IRQ and FIQ handler for diferent interrupts. To select the handler I am going to set corresponding bits in Interrupt Security Registers (ICDISR), but I am going to use only secure world. Will it work?
    I expect to catch non-secure interrupt by interrupt handler in secure world, but I can't do it. I see that Highest Pending Interrupt Register (ICCHPIR) doesn't get ID of non-secure interrupt, despite non-secure interrupts are enabled in CPU Interface Control Register (ICCICR) and interrupt has pending status in the distributor.  Has anybody done something similar?
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