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ARM shifting instruction with register shift length

pgbackup pgbackup
Note: This was originally posted on 26th October 2009 at http://forums.arm.com

Hi,

For fun, I'm trying to write RTL for my own processor implementing the ARM v4 ISA. I have a question regarding the ARM shifting operation. In one of the addressing mode, I see that it is possible to get the shift length from a "fourth" register RS. (RN= first operand, RM=second operand, RD = destination). Thus, RM will be shifted depending upon the value of RS[7:0].

My question is how is this done? All the docs/books that I have been reading indicate that the register file has two read ports/one write ports for all register and three read/two write ports for the PC counter (r15). In the floor plan of the book by Furber, I see only a PC bus, A/B bus, and ALU result bus. The only way I can think about getting RS is the register file will have to have another port for this third operand in the register access stage. However, its seems that this port will only be utilized by the shifting operation and never be used in other instructions. Is there something I'm missing here?

I was thinking of implementing the class 5 stage pipeline except break down the execute into two stage: shift operand calculation + ALU.  Thanks for any information.

Kind regards.
Parents
  • Note: This was originally posted on 27th October 2009 at http://forums.arm.com

    You have an interesting idea of fun. 

    You might have to split the operation over two cycles.  You could check the cycle timings in the ARM TRMs, this might give indication of whether they use this approach.

    Just an observation, but you might find that the architecture is protected by various patents.


    Hi,

    Thanks. Looks like it does indeed take 2 cycles as per TRM so that makes sense now. Regarding patents, sure but I have no plans to do anything worthwhile with the code. Just a plain learning exercise....
Reply
  • Note: This was originally posted on 27th October 2009 at http://forums.arm.com

    You have an interesting idea of fun. 

    You might have to split the operation over two cycles.  You could check the cycle timings in the ARM TRMs, this might give indication of whether they use this approach.

    Just an observation, but you might find that the architecture is protected by various patents.


    Hi,

    Thanks. Looks like it does indeed take 2 cycles as per TRM so that makes sense now. Regarding patents, sure but I have no plans to do anything worthwhile with the code. Just a plain learning exercise....
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