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Data Flow diagram in Sloss book, ARM Development

Sean de grae
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Note: This was originally posted on 20th October 2009 at http://forums.arm.com

Hi to all on the ARM forum,

I'm new to ARM and have some questions:

The DATA FLOW diagram in the Sloss book, Arm Development, has several connections/buses which do not exist in the ARM documentation ( as far as I can see ).

They are :(1) connection direct from the MAC to the ALU bus
(2) a bus from the Register File direct to the MAC labeled Acc ( Accumulator bus )

ARM documents indicate that the MAC connects ONLY between the A and B buses

Can someone explain where I am  misinterpreting , or missing the point somewhere ?

Any help will be very much appreciated, thanks
Skippy
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    Note: This was originally posted on 30th October 2009 at http://forums.arm.com

    Thanks Iso for your response.

    I have searched high and low ( google ) since your post for schematics, implementation specific diagrams, etc but to no avail.

    I take your point re. the cycle times being best hint as to implementation. And, as you point out I don't need that info. to program the device anyway --- was just curious as to how exactly it was organised.

    Thanks again, Skippy
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  • Offline
    Note: This was originally posted on 30th October 2009 at http://forums.arm.com

    Thanks Iso for your response.

    I have searched high and low ( google ) since your post for schematics, implementation specific diagrams, etc but to no avail.

    I take your point re. the cycle times being best hint as to implementation. And, as you point out I don't need that info. to program the device anyway --- was just curious as to how exactly it was organised.

    Thanks again, Skippy
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