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I am working with an LS1043A (NXP) branded ARMv8 A53. I am trying to bring the board up in a secure way requiring me to write to a few configuration registers before releasing the CPU (for testing purposes). The steps outlined for a similar NXP device (LS1021) uses their toolchain (Code Warrior/Core Warrior TAP) to connect to the device under reset and write to memory. I reached out to NXP and was redirected to the DS5/DSTREAM community.
In short, when the CPU cores are being held in reset how can we configure DS5 to have read/write access to memory? Specifically, I am interested in the registers of the Security Fuse Processor (SFP) which are contained in the CCSR block, if the access region makes any difference.
What I am seeing in DS5 is the following:
oncepragmatic,
The default memory space is essentially virtual addressing, in the current exception level and security state. DS-5 is designed from the perspective that it'll be debugging ARM cores so it will try and access through the core. If the cores are powered down or in reset, it will simply fail.
Using AHB_0: as a prefix, then, will get you to where you want to go. The HPROT= value (as in AHB_0:<HPROT=nnn>) is the top 8 bits of the AHB-AP.CSW register. I'm actually a little nonplussed about the '67' value you mentioned is 0x43 which corresponds to SProt=1, Prot=3 which is basically Secure, Privileged, Data.
Should work. Again, though, be careful
Ta,
Matt