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AXD cycle count problems

setose setose
Note: This was originally posted on 23rd September 2009 at http://forums.arm.com

Hello everyone,
I recently use the AXD to study the instruction cycle of ARM926EJ-S processor.
Since it's said that ARM9EJ-S is the core of ARM926EJ-S,
I use both of the model to see the cycle count, and have some problems with them.

Here is the information from AXD with ARM9EJ-S:
~~~~~~~~~~~~~~~~instruction~~CoreCycle~~IDCycle~~IBus~~Idle~~DBus~~Total
add r8, pc, #0xc4~~~~~~1~~~~~~~~~4~~~~~~~~0~~~~~~3~~~~1~~~~0~~~~~4
ldmia r8, {r0,r1} ~~~~~~~2~~~~~~~~~6~~~~~~~~0~~~~~~4~~~~1~~~~1~~~~~6  

And the information with ARM9EJ-S is shown below:
~~~~~~~~~~~~~~~~instruction~~CoreCycle~~SEQ~~NONSEQ~~Idle~~Busy~~Total
add r8, pc, #0xc4~~~~~~1~~~~~~~~~4~~~~~~~~2~~~~~~2~~~~~~4~~~~0~~~~~8
ldmia r8, {r0,r1} ~~~~~~~2~~~~~~~~~6~~~~~~~~7~~~~~~3~~~~~~4~~~~0~~~~~14  

I suppose that it's reasonable for the same CoreCycle count, since the core processor architecture is the same.
However, use instruction 1 as an example,
it's quite strange that when ARM9EJ-S issue 3 memory request, (I suppose that it's because of the PCs sent out)
the ARM926EJ-S issue 2 SEQ and 2 NONSEQ request with the same instruction executed...
For the instruction 2 it becomes stranger that 5 SEQ and 1 NONSEQ requests are sent out in ARM926EJ-S!

I would expect that the IDCycle+IBus+DBus from ARM9EJ-S will somehow equal to the SEQ+NONSEQ from ARM926EJ-S, but it doesn't !
Can anyone tell me that is there anything I misunderstand with the information?
Thanks a lot!
Parents
  • Arm Employee Badge
    Note: This was originally posted on 24th September 2009 at http://forums.arm.com

    > First of all the number "NONSEQ" in instruction 1 bother me, since I'm wondering why there is two "NONSEQ" if it just prefetches the instructions.

    Is the MMU and cache enabled in your test case?

    If so, then you may be seeing accesses caused by the MMU page table walks rather than just the instruction fetch.

    > Second, for instruction 3, 4, 5, it seems strange to me that no bus activities during that time (no instruction prefetch?)

    Well, if the instruction cache line has already been loaded by the first access, then there will be no need for the core to access external memory (up to 8 instructions will be in the cache line loaded, depending on the alignment of the code, if the cache is enabled).
Reply
  • Arm Employee Badge
    Note: This was originally posted on 24th September 2009 at http://forums.arm.com

    > First of all the number "NONSEQ" in instruction 1 bother me, since I'm wondering why there is two "NONSEQ" if it just prefetches the instructions.

    Is the MMU and cache enabled in your test case?

    If so, then you may be seeing accesses caused by the MMU page table walks rather than just the instruction fetch.

    > Second, for instruction 3, 4, 5, it seems strange to me that no bus activities during that time (no instruction prefetch?)

    Well, if the instruction cache line has already been loaded by the first access, then there will be no need for the core to access external memory (up to 8 instructions will be in the cache line loaded, depending on the alignment of the code, if the cache is enabled).
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