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AXD cycle count problems

setose setose
Note: This was originally posted on 23rd September 2009 at http://forums.arm.com

Hello everyone,
I recently use the AXD to study the instruction cycle of ARM926EJ-S processor.
Since it's said that ARM9EJ-S is the core of ARM926EJ-S,
I use both of the model to see the cycle count, and have some problems with them.

Here is the information from AXD with ARM9EJ-S:
~~~~~~~~~~~~~~~~instruction~~CoreCycle~~IDCycle~~IBus~~Idle~~DBus~~Total
add r8, pc, #0xc4~~~~~~1~~~~~~~~~4~~~~~~~~0~~~~~~3~~~~1~~~~0~~~~~4
ldmia r8, {r0,r1} ~~~~~~~2~~~~~~~~~6~~~~~~~~0~~~~~~4~~~~1~~~~1~~~~~6  

And the information with ARM9EJ-S is shown below:
~~~~~~~~~~~~~~~~instruction~~CoreCycle~~SEQ~~NONSEQ~~Idle~~Busy~~Total
add r8, pc, #0xc4~~~~~~1~~~~~~~~~4~~~~~~~~2~~~~~~2~~~~~~4~~~~0~~~~~8
ldmia r8, {r0,r1} ~~~~~~~2~~~~~~~~~6~~~~~~~~7~~~~~~3~~~~~~4~~~~0~~~~~14  

I suppose that it's reasonable for the same CoreCycle count, since the core processor architecture is the same.
However, use instruction 1 as an example,
it's quite strange that when ARM9EJ-S issue 3 memory request, (I suppose that it's because of the PCs sent out)
the ARM926EJ-S issue 2 SEQ and 2 NONSEQ request with the same instruction executed...
For the instruction 2 it becomes stranger that 5 SEQ and 1 NONSEQ requests are sent out in ARM926EJ-S!

I would expect that the IDCycle+IBus+DBus from ARM9EJ-S will somehow equal to the SEQ+NONSEQ from ARM926EJ-S, but it doesn't !
Can anyone tell me that is there anything I misunderstand with the information?
Thanks a lot!
Parents
  • Note: This was originally posted on 25th September 2009 at http://forums.arm.com

    Thanks for the reply, but I still cannot explain the reason of the unchanged IDLE value.
    Furthermore, after I turn off the Icache, Dcache and MMU, it still seems strange to me.
    The number of cycle becomes:

    ~~~~~~~~~~~~~~~~instruction~~CoreCycle~~SEQ~~NONSEQ~~Idle~~Busy~~Total
    add r8, pc, #0xc4~~~~~~1~~~~~~~~~~4~~~~~~~~2~~~~~~1~~~~~~2~~~~0~~~~~5
    ldmia r8, {r0,r1} ~~~~~~~2~~~~~~~~~~6~~~~~~~~6~~~~~~3~~~~~~2~~~~0~~~~~11
    add r0,r0,r8~~~~~~~~~~3~~~~~~~~~~7~~~~~~~~7~~~~~~3~~~~~~2~~~~0~~~~~12
    add r1, r1, r8~~~~~~~~~4~~~~~~~~~~8~~~~~~~~7~~~~~~3~~~~~~2~~~~0~~~~~12
    sub r11. r0, #1~~~~~~~~5~~~~~~~~~9~~~~~~~~7~~~~~~3~~~~~~2~~~~0~~~~~12

    I suppose that the 1 NONSEQ and 2 SEQ in instruction 1 is the instruction fetch.
    However, for instruction 2, I cannot figure out why there are 2 NONSEQ there.
    I think that one of the NONSEQ is due to the ladmia, but how comes the other one? The fetch of instruction should be a SEQ one.
    Besides, since the instruction cache is turned off, it is strange to assume that the 4 new SEQ is due to instruction fetches since there should be no space for them.
    And for instruction 3, 4 & 5, the situations occur that all the number (SEQ, NONSEQ, Idle, Busy) unchanged.
    Where does the instruction come from at that time?

    Please give me some suggestions, thanks!
Reply
  • Note: This was originally posted on 25th September 2009 at http://forums.arm.com

    Thanks for the reply, but I still cannot explain the reason of the unchanged IDLE value.
    Furthermore, after I turn off the Icache, Dcache and MMU, it still seems strange to me.
    The number of cycle becomes:

    ~~~~~~~~~~~~~~~~instruction~~CoreCycle~~SEQ~~NONSEQ~~Idle~~Busy~~Total
    add r8, pc, #0xc4~~~~~~1~~~~~~~~~~4~~~~~~~~2~~~~~~1~~~~~~2~~~~0~~~~~5
    ldmia r8, {r0,r1} ~~~~~~~2~~~~~~~~~~6~~~~~~~~6~~~~~~3~~~~~~2~~~~0~~~~~11
    add r0,r0,r8~~~~~~~~~~3~~~~~~~~~~7~~~~~~~~7~~~~~~3~~~~~~2~~~~0~~~~~12
    add r1, r1, r8~~~~~~~~~4~~~~~~~~~~8~~~~~~~~7~~~~~~3~~~~~~2~~~~0~~~~~12
    sub r11. r0, #1~~~~~~~~5~~~~~~~~~9~~~~~~~~7~~~~~~3~~~~~~2~~~~0~~~~~12

    I suppose that the 1 NONSEQ and 2 SEQ in instruction 1 is the instruction fetch.
    However, for instruction 2, I cannot figure out why there are 2 NONSEQ there.
    I think that one of the NONSEQ is due to the ladmia, but how comes the other one? The fetch of instruction should be a SEQ one.
    Besides, since the instruction cache is turned off, it is strange to assume that the 4 new SEQ is due to instruction fetches since there should be no space for them.
    And for instruction 3, 4 & 5, the situations occur that all the number (SEQ, NONSEQ, Idle, Busy) unchanged.
    Where does the instruction come from at that time?

    Please give me some suggestions, thanks!
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