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AXD cycle count problems

setose setose
Note: This was originally posted on 23rd September 2009 at http://forums.arm.com

Hello everyone,
I recently use the AXD to study the instruction cycle of ARM926EJ-S processor.
Since it's said that ARM9EJ-S is the core of ARM926EJ-S,
I use both of the model to see the cycle count, and have some problems with them.

Here is the information from AXD with ARM9EJ-S:
~~~~~~~~~~~~~~~~instruction~~CoreCycle~~IDCycle~~IBus~~Idle~~DBus~~Total
add r8, pc, #0xc4~~~~~~1~~~~~~~~~4~~~~~~~~0~~~~~~3~~~~1~~~~0~~~~~4
ldmia r8, {r0,r1} ~~~~~~~2~~~~~~~~~6~~~~~~~~0~~~~~~4~~~~1~~~~1~~~~~6  

And the information with ARM9EJ-S is shown below:
~~~~~~~~~~~~~~~~instruction~~CoreCycle~~SEQ~~NONSEQ~~Idle~~Busy~~Total
add r8, pc, #0xc4~~~~~~1~~~~~~~~~4~~~~~~~~2~~~~~~2~~~~~~4~~~~0~~~~~8
ldmia r8, {r0,r1} ~~~~~~~2~~~~~~~~~6~~~~~~~~7~~~~~~3~~~~~~4~~~~0~~~~~14  

I suppose that it's reasonable for the same CoreCycle count, since the core processor architecture is the same.
However, use instruction 1 as an example,
it's quite strange that when ARM9EJ-S issue 3 memory request, (I suppose that it's because of the PCs sent out)
the ARM926EJ-S issue 2 SEQ and 2 NONSEQ request with the same instruction executed...
For the instruction 2 it becomes stranger that 5 SEQ and 1 NONSEQ requests are sent out in ARM926EJ-S!

I would expect that the IDCycle+IBus+DBus from ARM9EJ-S will somehow equal to the SEQ+NONSEQ from ARM926EJ-S, but it doesn't !
Can anyone tell me that is there anything I misunderstand with the information?
Thanks a lot!
Parents
  • Note: This was originally posted on 24th September 2009 at http://forums.arm.com

    Actually I want to know what the number shown in the "debug internal" means.
    Since I cannot find any document to explain how the number "SEQ" "NONSEQ" "IDLE" comes in ARM926EJ-S,
    I suppose that the number might have some relationships between those in ARM9EJ-S, but it seems that I am wrong.

    Besides, when I just examine about the number from ARM926EJ-S, another problem bothers me.
    I just list the scenario below:
    ~~~~~~~~~~~~~~~~instruction~~CoreCycle~~SEQ~~NONSEQ~~Idle~~Busy~~Total
    add r8, pc, #0xc4~~~~~~1~~~~~~~~~4~~~~~~~~2~~~~~~2~~~~~~4~~~~0~~~~~8
    ldmia r8, {r0,r1} ~~~~~~~2~~~~~~~~~6~~~~~~~~7~~~~~~3~~~~~~4~~~~0~~~~~14
    add r0,r0,r8~~~~~~~~~~3~~~~~~~~~7~~~~~~~~8~~~~~~3~~~~~~4~~~~0~~~~~15
    add r1, r1, r8~~~~~~~~~4~~~~~~~~~8~~~~~~~~8~~~~~~3~~~~~~4~~~~0~~~~~15
    subr11. r0, #1~~~~~~~~5~~~~~~~~~9~~~~~~~~8~~~~~~3~~~~~~4~~~~0~~~~~15

    First of all the number  "NONSEQ" in instruction 1 bother me, since I'm wondering why there is two "NONSEQ" if it just prefetches the instructions.
    Second, for instruction 3, 4, 5, it seems strange to me that no bus activities during that time (no insturction prefetch?).
    Besides, "Idle" term do not change at the same time. What's it about if no SEQ and no NONSEQ, and Idle does not change as well?
    I just cannot understand what's the actual meaning of the number "TOTAL" since its value equals SEQ+NONSEQ+Idle+Busy?

    ps: Some materials said that TOTAL is used to profile the total instruction of a function consumes.
    However I cannot find out  why from this scenario.

    Can someone give me some suggestions?
    Thanks a lot!
Reply
  • Note: This was originally posted on 24th September 2009 at http://forums.arm.com

    Actually I want to know what the number shown in the "debug internal" means.
    Since I cannot find any document to explain how the number "SEQ" "NONSEQ" "IDLE" comes in ARM926EJ-S,
    I suppose that the number might have some relationships between those in ARM9EJ-S, but it seems that I am wrong.

    Besides, when I just examine about the number from ARM926EJ-S, another problem bothers me.
    I just list the scenario below:
    ~~~~~~~~~~~~~~~~instruction~~CoreCycle~~SEQ~~NONSEQ~~Idle~~Busy~~Total
    add r8, pc, #0xc4~~~~~~1~~~~~~~~~4~~~~~~~~2~~~~~~2~~~~~~4~~~~0~~~~~8
    ldmia r8, {r0,r1} ~~~~~~~2~~~~~~~~~6~~~~~~~~7~~~~~~3~~~~~~4~~~~0~~~~~14
    add r0,r0,r8~~~~~~~~~~3~~~~~~~~~7~~~~~~~~8~~~~~~3~~~~~~4~~~~0~~~~~15
    add r1, r1, r8~~~~~~~~~4~~~~~~~~~8~~~~~~~~8~~~~~~3~~~~~~4~~~~0~~~~~15
    subr11. r0, #1~~~~~~~~5~~~~~~~~~9~~~~~~~~8~~~~~~3~~~~~~4~~~~0~~~~~15

    First of all the number  "NONSEQ" in instruction 1 bother me, since I'm wondering why there is two "NONSEQ" if it just prefetches the instructions.
    Second, for instruction 3, 4, 5, it seems strange to me that no bus activities during that time (no insturction prefetch?).
    Besides, "Idle" term do not change at the same time. What's it about if no SEQ and no NONSEQ, and Idle does not change as well?
    I just cannot understand what's the actual meaning of the number "TOTAL" since its value equals SEQ+NONSEQ+Idle+Busy?

    ps: Some materials said that TOTAL is used to profile the total instruction of a function consumes.
    However I cannot find out  why from this scenario.

    Can someone give me some suggestions?
    Thanks a lot!
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