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Pipeline issue on return from FIQ

Freddy Freddy
Note: This was originally posted on 17th August 2009 at http://forums.arm.com

I'm using an ARM9 (Cirrus EP9302). My FIQ interrupt handler returns using "subs pc, lr, #4" instruction. The way the handler was originally written, the previous instruction was an "str r9,[r8]" with r8 pointing to some I/O. This version crashes in all kinds of ways. Inserting one "nop" instruction, before the "subs" solves the problem.

This looks to me (but I'm not sure) as if the switching of the FIQ registers happens while the "str" instruction is still in progress, and it stores to whatever address the normal (supervisor) mode r8 points to. I could not find any documentation of the pipeline behavior during return from FIQ interrupt.

I have a working solution, but I don't like when I don't understand how it works. It may rise again behind me and bite...

Any help?
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  • Arm Employee Badge
    Note: This was originally posted on 21st August 2009 at http://forums.arm.com

    The only generic (and completely inappropriate in real applications) way to tell, is to poll the interrupt status in the interrupt controller itself until the corresponding bit indicates the signal has been deasserted, before returning from the ISR.


    Even this is flawed in multiple ways; for a random interrupt source this scheme will likely result in deadlock as it is not possible to tell the difference between the interrupt not having yet been cleared vs it having become near instantaneously repended via a new event; secondly there is no guaranteed delay between the interrupt controller and the actual processor interrupt pin, thus reading the bit being clear and the same information arriving at the processor's interrupt decision logic may still be decoupled by a few cycles.

    The only generic scheme is to clear the source as early as possible, and for software to support spurious interrupts.

    hth
    s.
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  • Arm Employee Badge
    Note: This was originally posted on 21st August 2009 at http://forums.arm.com

    The only generic (and completely inappropriate in real applications) way to tell, is to poll the interrupt status in the interrupt controller itself until the corresponding bit indicates the signal has been deasserted, before returning from the ISR.


    Even this is flawed in multiple ways; for a random interrupt source this scheme will likely result in deadlock as it is not possible to tell the difference between the interrupt not having yet been cleared vs it having become near instantaneously repended via a new event; secondly there is no guaranteed delay between the interrupt controller and the actual processor interrupt pin, thus reading the bit being clear and the same information arriving at the processor's interrupt decision logic may still be decoupled by a few cycles.

    The only generic scheme is to clear the source as early as possible, and for software to support spurious interrupts.

    hth
    s.
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