• Locked Locked
  • Replies 7 replies
  • Subscribers 119 subscribers
  • Views 5119 views
  • Users 0 members are here
Options
Related
How was your experience today?
This discussion has been locked.
You can no longer post new replies to this discussion. If you have a question you can start a new discussion

Pipeline issue on return from FIQ

Freddy Freddy
Note: This was originally posted on 17th August 2009 at http://forums.arm.com

I'm using an ARM9 (Cirrus EP9302). My FIQ interrupt handler returns using "subs pc, lr, #4" instruction. The way the handler was originally written, the previous instruction was an "str r9,[r8]" with r8 pointing to some I/O. This version crashes in all kinds of ways. Inserting one "nop" instruction, before the "subs" solves the problem.

This looks to me (but I'm not sure) as if the switching of the FIQ registers happens while the "str" instruction is still in progress, and it stores to whatever address the normal (supervisor) mode r8 points to. I could not find any documentation of the pipeline behavior during return from FIQ interrupt.

I have a working solution, but I don't like when I don't understand how it works. It may rise again behind me and bite...

Any help?
Parents
  • Arm Employee Badge
    Note: This was originally posted on 18th August 2009 at http://forums.arm.com

    I think that unlikely, as on the ARM9 all instructions are issued and executed in order.  So the STR instruction will be being executed while the SUBS is still decoding.

    My guess would be timing.  What does the STR do?  Clear the source of the interrupt?  If so, its possible that the write is not completing on the bus before the exception return.  Potentially meaning that you re-take the exception.
Reply
  • Arm Employee Badge
    Note: This was originally posted on 18th August 2009 at http://forums.arm.com

    I think that unlikely, as on the ARM9 all instructions are issued and executed in order.  So the STR instruction will be being executed while the SUBS is still decoding.

    My guess would be timing.  What does the STR do?  Clear the source of the interrupt?  If so, its possible that the write is not completing on the bus before the exception return.  Potentially meaning that you re-take the exception.
Children
No data