• Locked Locked
  • Replies 7 replies
  • Subscribers 119 subscribers
  • Views 5122 views
  • Users 0 members are here
Options
Related
How was your experience today?
This discussion has been locked.
You can no longer post new replies to this discussion. If you have a question you can start a new discussion

Pipeline issue on return from FIQ

Freddy Freddy
Note: This was originally posted on 17th August 2009 at http://forums.arm.com

I'm using an ARM9 (Cirrus EP9302). My FIQ interrupt handler returns using "subs pc, lr, #4" instruction. The way the handler was originally written, the previous instruction was an "str r9,[r8]" with r8 pointing to some I/O. This version crashes in all kinds of ways. Inserting one "nop" instruction, before the "subs" solves the problem.

This looks to me (but I'm not sure) as if the switching of the FIQ registers happens while the "str" instruction is still in progress, and it stores to whatever address the normal (supervisor) mode r8 points to. I could not find any documentation of the pipeline behavior during return from FIQ interrupt.

I have a working solution, but I don't like when I don't understand how it works. It may rise again behind me and bite...

Any help?
Parents
  • Note: This was originally posted on 21st August 2009 at http://forums.arm.com

    Eliminating the "nop" saved one cycle, which is significant for a handler executing as often as mine.

    Sure, what I meant with "no better than" was that placing the write at an arbitrary distance from the return until it happens to work in a given situation still lacks formal proof that this won't bite you later. Don't get me wrong, I am sure what you are doing is perfectly fine for all practical purposes. But the issue involves more than just the pipeline hazard described here: [url="http://infocenter.arm.com/help/topic/com.arm.doc.faqs/ka3788.html"]http://infocenter.arm.com/help/topic/com.a...aqs/ka3788.html[/url]

    In general, we cannot tell how long the (maximum) latency is, between writing to the interrupt-clear register in a device, and the interrupt controller registering this fact, unless the device vendor tells us (which they rarely do).

    The only generic (and completely inappropriate in real applications) way to tell, is to poll the interrupt status in the interrupt controller itself until the corresponding bit indicates the signal has been deasserted, before returning from the ISR.

    Best regards
    Marcus
Reply
  • Note: This was originally posted on 21st August 2009 at http://forums.arm.com

    Eliminating the "nop" saved one cycle, which is significant for a handler executing as often as mine.

    Sure, what I meant with "no better than" was that placing the write at an arbitrary distance from the return until it happens to work in a given situation still lacks formal proof that this won't bite you later. Don't get me wrong, I am sure what you are doing is perfectly fine for all practical purposes. But the issue involves more than just the pipeline hazard described here: [url="http://infocenter.arm.com/help/topic/com.arm.doc.faqs/ka3788.html"]http://infocenter.arm.com/help/topic/com.a...aqs/ka3788.html[/url]

    In general, we cannot tell how long the (maximum) latency is, between writing to the interrupt-clear register in a device, and the interrupt controller registering this fact, unless the device vendor tells us (which they rarely do).

    The only generic (and completely inappropriate in real applications) way to tell, is to poll the interrupt status in the interrupt controller itself until the corresponding bit indicates the signal has been deasserted, before returning from the ISR.

    Best regards
    Marcus
Children
No data