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ARM cache in simulator

ManishKesarkar ManishKesarkar
Note: This was originally posted on 27th July 2009 at http://forums.arm.com

Hi
I am using RVDS 4.0 Real view Instruction set simulator for ARM926EJS target. While configuring the target using ARMulator dialog box I get option MMU/MPU initialization when I select this option I get 60 % reduction in total cycles for my code.  When this option is not selected the code for cache enabling is included it has no effect and I 60% increase in cycles is observed.  So does this option enables cache does and uses  default MMU/MPU tables for cache?

The core configuration I am using is as follows
ARM926EJ-S, 16Kb I-cache, 16Kb D-cache, 64Kb I-Ram, 64KB D-Ram,
Memory Management Unit, I-uTLB, D-uTLB, TLB, BIU, Little endian,
Debug Comms Channel, 4GB, Pagetables, Mapfile, Timer, Profiler,
SIMRDI MemCallback, Tube, Millisecond [6666.67 cycles_per_millisecond], IntCtrl,

Also in above waht does figure [6666.67 cycles_per_millisecond] indicates?
  • Note: This was originally posted on 27th July 2009 at http://forums.arm.com

    In the second scenario are you just enabling the caches, or also configurring the MMU?  On the 926 all data accesses are treated as non-cacheable while the MMU is disabled.

    Are you using RVDS?  If so, you should have a 926 MMU/cache initialization example included.


    I am using RVDS and I am just added cache enabling code. I have not added MMU initialization code.  I will try that.
  • Arm Employee Badge
    Note: This was originally posted on 27th July 2009 at http://forums.arm.com

    In the second scenario are you just enabling the caches, or also configurring the MMU?  On the 926 all data accesses are treated as non-cacheable while the MMU is disabled.

    Are you using RVDS?  If so, you should have a 926 MMU/cache initialization example included.