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Cortex M3 - how to enter Privileged Mode?

Sebastian Gaertner
Note: This was originally posted on 15th July 2009 at http://forums.arm.com

Hi,

I try to get an implementation that disables all interrupts up to an specific level. I use the BASEPRI for this.
However the disabling doesnt work, all interrupts are passing through like before.

At the moment of entering the disabling function the CONTROL register is "0x00".
Now what means 0x00? The Cortex TRM says
CONTROL[0] = 0 is user mode and
CONTROL[0] = 1 is privileged mode.
And the book "The Definitive Guide to the Arm Cortex-M3" says it mixed up:
CONTROL[0] = 1 is user mode and
CONTROL[0] = 0 is privileged mode.

I expect the information in the TRM is the right... is it?

I wonder why my debugger is showing the CONTROL = 0x00 at reset of the device. Should not normally the device start in privileged mode?
Does anyone work with a Cortex M3 and can confirm that?
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  • Note: This was originally posted on 16th July 2009 at http://forums.arm.com

    Hi Joseph

    thanks for the hints with the priorities, I understand better now. Seems my priority  is still set to 0 - so I see still the interrupt.

    Yes, here we have two different versions of the CONTROl[0] description. This is a part of the TRM I used:

    Cortex™-M3 TRM Revision: r1p1:

    Thread mode is privileged out of reset, but you can change it to user or unprivileged by
    clearing the CONTROL[0] bit using the MSR instruction.
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  • Note: This was originally posted on 16th July 2009 at http://forums.arm.com

    Hi Joseph

    thanks for the hints with the priorities, I understand better now. Seems my priority  is still set to 0 - so I see still the interrupt.

    Yes, here we have two different versions of the CONTROl[0] description. This is a part of the TRM I used:

    Cortex™-M3 TRM Revision: r1p1:

    Thread mode is privileged out of reset, but you can change it to user or unprivileged by
    clearing the CONTROL[0] bit using the MSR instruction.
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