Hi everyone,
When I am auto configuring my custom platform, DS-5 is able to see all the ARM chain like this:
-In info dialogue:
info: Opening the debug pre-connection to device 1
info: Powering up the DAP
info: Connecting to the DAP
info: Detecting AP buses
info: DAP_CONFIG_INFO = 1,00:H
info: Found AHB-AP on AP0
info: Looking for ROM tables on AP 0
info: Reading ROM table for AHB-AP at AP index 0 :-
info: ROM table base address = 0xE00FF000
info: End of ROM table
info: No platforms found that match
-
The following information shows the logging output when connecting to an RVI unit and autconfiguring :rvi_lob_client.exe
***********
Process List built. Connected and waiting for logging.
fpgad warning No connection specified to disable.
traced error Probe error: No supported trace connector
rifsd error CRIFSCmdProc::CommandFILEOPEN open failed file(/real-ice
/backup/_version_) errno=2 {No such file or directory}
serverd warning CArmDP_TPlateV2::SetIgnorePowerUpFail: has been configur
ed to ignore a power up failure
serverd error AP is disabled [AP.CSW=00000000]
serverd error LastErr[0] +++ AP_AxB_ReadMemBlock failed - DAP error.
serverd error Failed to read memory
serverd error DAPERR_AP_DISABLED : AP disabled - memory operation cann
ot continue.
usbd error CUsbServer: run in read error no 14
usbd error CUsbWriter: run Z thread exception -> Operation interrup
ted
serverd info /var/expbus_version_info does not exist
cfgqueryd info DSPROBE setting: Enabling ARM JTAG 20 (PIN_MODE = JTAG)
cfgqueryd info Activated debug connector 1
cfgqueryd info CJTAGDriver::DetectRTCLK did detect RTCLK
cfgqueryd info CFPGA_RVIHW::SetJTAGClock @ 50000000 Hz, using RTCK
cfgqueryd info CClkCtrl::SetJTAGClkFreq requested freq=50000000; using
freq=100000000 with FPGADiv=0
cfgqueryd info CRVIAutoDetect::MeasureDeviceCount measuring the length
of DR chain in BYPASS
cfgqueryd info DR Chain 0..01..1 filled[1024]: 000000000000000000000000
00000000000000000000000000000000000000000000000000000000000000000000000000000000
00000001111111111111111111111111111111111111111111111111111111111111111111111111
11111111111111111111111111111111111111111111111111111111111111111111111111111111
1111111111111111111111111111111111111110
cfgqueryd info CRVIAutoDetect::MeasureTotalDRLength Measured total DR l
ength as 1
cfgqueryd info CRVIAutoDetect::MeasureDeviceCount Measured JTAG device
count as 1
cfgqueryd info DR Chain after tap reset[32]: 00001011101000000001010001
110111
cfgqueryd info Device 0 has IDCODE = 0x0BA01477
cfgqueryd info CRVIAutoDetect::deviceCountForIDCode device count for ID
0x0BA01477 is 1
cfgqueryd info CRVIAutoDetect::MeasureScanChainLength returned 1 device
s
cfgqueryd info CRVIAutoDetect::autodetect_config measuring the total IR
length
cfgqueryd info IR Chain 1..10..0 filled[1024]: 111111111111111111111111
11110000000000000000000000000000000000000000000000000000000000000000000000000000
0000000000000000000000000000000000000001
cfgqueryd info CRVIAutoDetect::MeasureTotalIRLength Measured total IR l
ength as 4
cfgqueryd info CRVIAutoDetect::autodetect_config measured the total IR
length = 4
cfgqueryd info CRVIAutoDetect::autodetect_config measuring the number o
f taps
cfgqueryd info AutoDetect: get_ir_data, Dev 0 IRLen=4
cfgqueryd info CRVIAutoDetect::autodetect_config measured the number of
taps = 1
cfgqueryd info Device 0 detected as ARMCS-DP from ARM
cfgqueryd info CRVIAutoDetect::get_scan_chain_length Detecting length o
f scan chain 6
serverd info CFPGA_RVIHW::SetJTAGClock @ 50000000 Hz, using RTCK
serverd info CClkCtrl::SetJTAGClkFreq requested freq=50000000; using
serverd info DSPROBE setting: Enabling ARM JTAG 20 (PIN_MODE = JTAG)
serverd info Activated debug connector 1
serverd info Performing a TAP reset on init connect
serverd info Selected DP TTAP path: /real-ice/jtag-templates/arm/armj
tagdp/V1.0/
serverd info CTurboTAPExt: Using template '/real-ice/jtag-templates/a
rm/armjtagdp/V1.0/'
serverd info CTurboTAPExt: Using fixed-up turbotap files
serverd info CFPGA_RVIHW: Verified load of TurboTAP sequence file at
1:0x0000..0x1747
serverd info CArmDP_TPlateV2::DAPPowerControl: Starting Power Up sequ
ence
serverd info DP_PowerUp - Powering up the DAP
serverd info CArmDP_TPlateV2::DAPPowerControl: reading 1st AP IDR to
check power up successful
serverd info Determined AP type as AP_AHB_SWIFT
serverd info CArmDP_TPlateV2::DAPPowerControl: power up complete
serverd info rvmsgapi: TPlateConnect() -> 0x0000, Proc ID = 0xba01477
, RVM_CONSTATE=0x000A, TAPRstOnFirstConn = true
serverd info CArmDP_TPlateV2::DAPPowerControl: Starting Power down se
quence
serverd info DP_PowerDown - Powering down the DAP
serverd info CArmDP_TPlateV2::DAPPowerControl: Power down sequence co
mplete
**********
- However I can download .axf in debug Configuration for debugging. But I don't understand how the chain doesn't show up. I am new to DS-5 and FPGA, so many thank to help me understand and fix this problem!
Hi,
Sorry to hear about the problems that you have been having with the configuration of your target using the Dbghw_config tool.
From your information, I can see that :
- a DAP (Debug Access Port) has been correctly identified
- there is 1 Access Port, AHB-AP on AP0
- there is a CoreSight ROM table apparently located at 0xE00FF000
- but the reading of the CoreSight ROM table fails
So it's the failure to read the CoreSight ROM table that is causing your target not to be detected because the tools can't determine what devices are on the target.
I can work out that your target is a Cortex-M processor, but as the CoreSight ROM table read is apparently failing, the topology cannot be determined.
The Dbghw_config tool is actually deprecated in DS-5 and has been replaced by the Platform Configuration Editor (PCE) from DS-5 v5.21 onwards.
Can I suggest that you try using PCE to auto-detect the target and determine its' topology ?
You can find a guide on how to do this at :
Developer Resources / Tutorials / SoC Bring-Up Using the Platform Configuration Editor (PCE) | ARM DS-5 Development Stu…
Please work through this and let me know what your results are.
For reference, I have done the same with a known working Cortex-M3 platform and I have attached a couple of screenshots from DS-5 v5.23.1 PCE below :
The screenshot below shows the detail of the read of the CoreSight ROM table. This may be useful for debugging the issue on your platform.
You can see that the individual CoreSight ROM table entries that are valid (bit[0] = b1) are listed and then PCE will go to each of the address offsets listed as 'valid' and then perform a memory read to determine the devices located there.
Once the devices have been completed, it will then attempt to determine the the topology of the platform.
So please try PCE and let us know how you get on.
I look forward to hearing from you.
Regards,
Stuart
Is everything working now ?
Do please let me know how you are getting on.