• Locked Locked
  • Replies 8 replies
  • Subscribers 119 subscribers
  • Views 11472 views
  • Users 0 members are here
2025 survey

We are running a survey to help us improve the experience for all of our members. If you see the survey appear, please take the time to tell us about your experience if you can.

Options
Related
How was your experience today?
This discussion has been locked.
You can no longer post new replies to this discussion. If you have a question you can start a new discussion

Program Counter update

Maya Maya
Note: This was originally posted on 15th June 2009 at http://forums.arm.com

In the Architectural Reference Manual for ARMv7 the PC update is described such that it gets update with adding 8 to the current PC while executing an ARM instruction and adding 4 for Thumb instruction. ARM instructions are 32-bit, hence I'd expect the PC to be updated by adding 4 to it rather than 8. Does anyone knows what is the reason behind this? Am I missing something or is it a mistake?

Thanks
Parents
  • Arm Employee Badge
    Note: This was originally posted on 16th June 2009 at http://forums.arm.com

    Can provide a page number in the ARM ARM so I can be sure what you are talking about?

    The PC increment during "normal execution" will be 4 for ARM, and 2 or 4 for Thumb (depending if if it is a 16 or 32-bit Thumb instruction).

    I think the numbers you are referring to the exception offsets, which are used to calculate the address of the faulting instruction or the address of the instruction to return to after an exception has occurred. For historical reasons these offsets are the sometimes numbers you describe - the full set of offsets is described in Table 10.4. of the ARM ARMv7-AR.
Reply
  • Arm Employee Badge
    Note: This was originally posted on 16th June 2009 at http://forums.arm.com

    Can provide a page number in the ARM ARM so I can be sure what you are talking about?

    The PC increment during "normal execution" will be 4 for ARM, and 2 or 4 for Thumb (depending if if it is a 16 or 32-bit Thumb instruction).

    I think the numbers you are referring to the exception offsets, which are used to calculate the address of the faulting instruction or the address of the instruction to return to after an exception has occurred. For historical reasons these offsets are the sometimes numbers you describe - the full set of offsets is described in Table 10.4. of the ARM ARMv7-AR.
Children
No data