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ARM Vs GCC assembler

Gerald Murphy
Note: This was originally posted on 25th January 2013 at http://forums.arm.com

Hi,

I have a question regarding the ARM and GCC assemblers i.e. ARMASM and GAS.

MOV.W R4,#0x87C0 is translated to F248_74C0 by ARMASM.

However, GAS throws up the error "invalid constant (87c0) after fixup" for the same instruction. Why does GAS give an error for this?

I realise the operand is 16-bit but I'm using the '.syntax unified'. I thought GAS supports .W and .N suffixes. Even without the .W suffix, GAS gives the same error whereas ARMASM quietly expands the 16-bit instruction to 32-bit.

I'm using 'GCC version 4.7.2 (Sourcety CodeBench Lite 2012.09-63).

Any insight as to why GAS is giving an error is appreciated. The workaround is to use two instructions. The following 2 instructions compile OK.

MOVW  R4  ,#0xC0
MOVT R4  ,#0x87

Thanks and regards,
Ger
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  • Note: This was originally posted on 11th February 2013 at http://forums.arm.com

    Thanks for the explanation, it helped a lot. I now understand that the first 4 encodings (i:imm3a: = 0000x,0001x, 0010x,0011x) are special encodings for various 8-bit repeat combinations. The remaining i:iim3:a  encodings are used for shift operations (assuming MSB=1, 5-bit shift + 7-bit immediate).

    Unfortunately, I'm not familiar with the classic ARM ISA. The ARM Cortex-M3 (ARMV7) is my first introduction to ARM processors - so I'm learning as I go!

    Another feature I'm getting to grips with is the thumb-2 instruction set concept. While I realise that the thumb-2 instruction set is a combination of 16-bit (thumb) and 32-bit (ARM) instructions, I'm still a little unsure as to how the architecture handles thumb-2 instructions. The unified assembly langauge instruction set means that the same syntax is used for both 16-bit and 32-bit instructions. Here is my understanding (basic level) - feel free to correct any errors.

    Q1) I'm assuming the assembler will try to use the 16-bit instruction encoding whenever possible. Depending on the registers used, immediate value size, if .W is specified etc, the assember will use a 32-bit instruction encoding.

    Q2) Are all instructions decoded as 32-bit by the processor logic? If the first 5-bits [15:11] of the instruction half-word are 0b11101, 0c11110 or 0b11111, the instruction is 32-bits. The 16-bit instructions are used to improve code density and are converted to 32-bit for execution.

    Q3) For the ARM V7 architecture with a 3-stage pipeline, the program counter value =  (address of current instruction being executed + 4). Does this still hold true even if an instruction is 32-bits? I assume it does but I'm unsure as to why it isn't = (address of current instruction + 6). 

    Regards,
    Ger
Reply
  • Note: This was originally posted on 11th February 2013 at http://forums.arm.com

    Thanks for the explanation, it helped a lot. I now understand that the first 4 encodings (i:imm3a: = 0000x,0001x, 0010x,0011x) are special encodings for various 8-bit repeat combinations. The remaining i:iim3:a  encodings are used for shift operations (assuming MSB=1, 5-bit shift + 7-bit immediate).

    Unfortunately, I'm not familiar with the classic ARM ISA. The ARM Cortex-M3 (ARMV7) is my first introduction to ARM processors - so I'm learning as I go!

    Another feature I'm getting to grips with is the thumb-2 instruction set concept. While I realise that the thumb-2 instruction set is a combination of 16-bit (thumb) and 32-bit (ARM) instructions, I'm still a little unsure as to how the architecture handles thumb-2 instructions. The unified assembly langauge instruction set means that the same syntax is used for both 16-bit and 32-bit instructions. Here is my understanding (basic level) - feel free to correct any errors.

    Q1) I'm assuming the assembler will try to use the 16-bit instruction encoding whenever possible. Depending on the registers used, immediate value size, if .W is specified etc, the assember will use a 32-bit instruction encoding.

    Q2) Are all instructions decoded as 32-bit by the processor logic? If the first 5-bits [15:11] of the instruction half-word are 0b11101, 0c11110 or 0b11111, the instruction is 32-bits. The 16-bit instructions are used to improve code density and are converted to 32-bit for execution.

    Q3) For the ARM V7 architecture with a 3-stage pipeline, the program counter value =  (address of current instruction being executed + 4). Does this still hold true even if an instruction is 32-bits? I assume it does but I'm unsure as to why it isn't = (address of current instruction + 6). 

    Regards,
    Ger
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