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Need help in GCC intrinsics for NEON

Kiran Kumar
Note: This was originally posted on 4th April 2012 at http://forums.arm.com

Hi All,


   Can somebody tell me what are the equivalent GCC and ARM intrinsics for generating the below NEON ASM statements?

vld3.16 {d0,d2,d4},[r0]!   
vld3.16 {d1,d3,d5},[r0]! 

Thanks,
Kiran
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  • Arm Employee Badge
    Note: This was originally posted on 10th April 2012 at http://forums.arm.com

    Half the point of intrinsics is that they hide register allocation as it's a good thing for the compiler to handle, and closely tied to instruction scheduling which is the other point of using them rather than asm.
    I can't see a way of directly doing what you want using intrinsics - you generally have to either cast the intrinsic structure type pointers and type-pun (which is probably bad on newer compilers with strict aliasing) - or memcpy fields between them to get things in the order you want. Unfortunately compilers don't really like the aliasing of d-registers to q-registers, so this tends to be one area the code gen suffers a bit in my experience.
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  • Arm Employee Badge
    Note: This was originally posted on 10th April 2012 at http://forums.arm.com

    Half the point of intrinsics is that they hide register allocation as it's a good thing for the compiler to handle, and closely tied to instruction scheduling which is the other point of using them rather than asm.
    I can't see a way of directly doing what you want using intrinsics - you generally have to either cast the intrinsic structure type pointers and type-pun (which is probably bad on newer compilers with strict aliasing) - or memcpy fields between them to get things in the order you want. Unfortunately compilers don't really like the aliasing of d-registers to q-registers, so this tends to be one area the code gen suffers a bit in my experience.
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