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i got really weird test result of memory barrier on Cortex A9

yitian bu
Parents
  • Arm Employee Badge
    Note: This was originally posted on 28th November 2011 at http://forums.arm.com

    [color=#222222][size=2]> how to get the result that in scenario 2 the cpu0("read thread") are blocked less time than in scenario 1 ?[/size][/color]
    [color=#222222][size=2]
    [/size][/color]
    [color=#222222][size=2]I'm not sure it necessarily is "less time" - it's just "different" and different enough that you hit the race condition more often. It's really hard to say what is actually happening inside the core as the internal micro-architecture is relatively complex (and I'm a software guy).[/size][/color]
    [color=#222222][size=2]
    [/size][/color]
    [size=2]The software without barriers is broken, so not worth spending too long explaining why it breaks a particular way, right ... =)[/size]
    [color=#222222][size=2]
    [/size][/color]
    [color=#222222][size=2]Cheers, [/size][/color]
    [color=#222222][size=2]Iso [/size][/color]
Reply
  • Arm Employee Badge
    Note: This was originally posted on 28th November 2011 at http://forums.arm.com

    [color=#222222][size=2]> how to get the result that in scenario 2 the cpu0("read thread") are blocked less time than in scenario 1 ?[/size][/color]
    [color=#222222][size=2]
    [/size][/color]
    [color=#222222][size=2]I'm not sure it necessarily is "less time" - it's just "different" and different enough that you hit the race condition more often. It's really hard to say what is actually happening inside the core as the internal micro-architecture is relatively complex (and I'm a software guy).[/size][/color]
    [color=#222222][size=2]
    [/size][/color]
    [size=2]The software without barriers is broken, so not worth spending too long explaining why it breaks a particular way, right ... =)[/size]
    [color=#222222][size=2]
    [/size][/color]
    [color=#222222][size=2]Cheers, [/size][/color]
    [color=#222222][size=2]Iso [/size][/color]
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