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Streamline: Consider removing some other events to make room (For CPU only six counters can be used related to BUS and Cache ) Is there a way to track all of them .

Omkar2895

Hardware used  : Khadas Vim3 

Application: CNN model

CPU: ARM cortex A73

I am not able to get values for more than 6 counters at a single run, for example from the following I'm able to record values only for counters in Bold if I need remaining values I have to rerun the test by replacing them. Is there a way I can use more than 6 counters related to cache /bus 

 BUS :

a.Access

b.Access(Device)

c.Access(Normal)

d.Access (Normal , Cachable , sharable)

e.Access (NOT NCS)

 Instruction (Execution) : 

a.All

b.Branch(Immediate)

c.Branch(Return)

d.Exception(Return)

e.Increment PMWINC register

f.Write to CONTEXTIDR

g.write to PC

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  • +1

    Is there a way I can use more than 6 counters related to cache /bus 

    Not in the current tool. Most Arm CPU hardware only has 6 physical counters implemented (plus a cycle counter), so that's a hard limit. In a future version of the tool we will implement software multiplexing to capture arbitrary numbers of counters with time-division multiplexing, but it's not yet planned for a specific release. 

    Kind regards, 
    Pete

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  • +1

    Is there a way I can use more than 6 counters related to cache /bus 

    Not in the current tool. Most Arm CPU hardware only has 6 physical counters implemented (plus a cycle counter), so that's a hard limit. In a future version of the tool we will implement software multiplexing to capture arbitrary numbers of counters with time-division multiplexing, but it's not yet planned for a specific release. 

    Kind regards, 
    Pete

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