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ARM ABI says that the stack should be 8-byte aligned, but the stack is sometimes aligned only to 4-byte boundary.
For example, I have the following simple busy-delay function:
void delay(int iter) { int volatile counter = 0; while (counter < iter) { // delay loop ++counter; }}
This compiles with IAR EWARM 9.10.2 to the following disassembly:
SUB SP, SP, #0x4...ADD SP, SP, #0x4BX LR
The problem is that after SUB SP,SP,4 the stack is misaligned (is aligned only to 4-byte boundary).
Why is this happening? Is this compliant with the ARM ABI? Are there any compiler options to control that?
Thanks a lot for explaining these questions!
This is a forum for Arm Development Studio users. Please can you submit your query to IAR or their forums directly.
However, for your comment, I do not believe this is true for 32-bit Arm processors (I assume you are using a Cortex-M processor?). It must be 8-byte aligned on interfaces (ie function calls or returns), but can be only word aligned within the function:
https://github.com/ARM-software/abi-aa/blob/60a8eb8c55e999d74dac5e368fc9d7e36e38dda4/aapcs32/aapcs32.rst#universal-stack-constraints
https://github.com/ARM-software/abi-aa/blob/60a8eb8c55e999d74dac5e368fc9d7e36e38dda4/aapcs32/aapcs32.rst#6212stack-constraints-at-a-public-interface