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Problem in generating position independent code with out TEXTREL

Note: This was originally posted on 12th August 2010 at http://forums.arm.com

Hi Experts,

Issue:Not able to remove TEXTREL from our static library generated with --apcs /fpic option using armcc(RVCT 4.0 build 771 tool chain)

Description:
We compiled our codebase(some modules with handwritten assembly) using armcc(RVCT 4.0 build 771 tool chain) to get static libraries, and then these are used by gstreamer module which further compiles using the above generated libraries with wrappers using GCC tool chain and creates shared objects(.so).

Even though we use equivalent --apcs /fpic compile time option during static library creation to remove position independent code, the TEXTREL are not going from library.
When we disable the (handwritten assembly) in the above mentioned codebase, TEXTRELs go away.
As there are lot of handwritten ARM assembly functions,its difficult to enable one by one and compile and check.

So,Experts please throw some light on this issue.

Thanks In Advance,
satish

Parents

Darisi V SATISH BABU over 12 years ago

Note: This was originally posted on 6th January 2011 at http://forums.arm.com

Hi Scott,

I need to use embedded assembly only. So, I had tested the sample code given by you and here are my observations:

The below mentioned PI version code is also generating TEXTREL's.....

__asm int foo_asm() { ldr r1, dlbl ulbl add r1, r1, pc ldr r0,[r1,r0,lsl #2] bx lr align dlbl dcd __cpp(table) - ulbl - 8 }

To analyze the behavior of arm compiler and embedded assembler, I had generated the test.tmp.s file from test.c file. I am unable to upload the files.There is error in uploading.So,i am copying the file contents:

test.c file content:
extern short int table_1[33]; int foo(int i) { return table_1[i]; } __asm int foo_asm(int i) { LDR r1, dlbl ulbl ADD r1, r1, pc LDR r0, [r1,r0,lsl #2] bx lr align dlbl DCD __cpp(table_1) - ulbl - 8 RELOC 96, table_1 //if this is used then only TEXTREL is not generated }

test.tmp.s file content - this is the .s file which is genrated by arm compiler for above code.
; generated by ARM NEON C/C++ Compiler, RVCT4.0 [Build 771] ; commandline armcc [--arm -c -S --gnu --no_hide_all --library_interface=aeabi_glibc -oobj/test.tmp.s --cpu=Cortex-A8 --fpu=VFPv3 --apcs=/interwork//fpic --no_unaligned_access -O3 -Otime --vectorize --enum_is_int --wchar32 obj/test.tmp.c] ARM REQUIRE8 PRESERVE8 AREA ||.text||, CODE, READONLY, ALIGN=2 ||foo|| PROC LDR r1,|L0.20| LDR r1,[pc,r1] ADD r0,r1,r0,LSL #1 LDRSH r0,[r0,#0] BX lr ENDP |L0.20| DCD 0x00000008 ;Line 18 RELOC 96, table_1 ;Line 19 AREA ||.arm_vfe_header||, DATA, READONLY, NOALLOC, ALIGN=2 DCD 0x00000000 ;*** Start embedded assembler *** #line 1 "obj/test.tmp.c" AREA ||.emb_text||, CODE, READONLY ARM EXPORT |foo_asm| [DYNAMIC] IMPORT |table_1| [DYNAMIC] #line 10 |foo_asm| PROC #line 11 LDR r1, dlbl ulbl ADD r1, r1, pc LDR r0, [r1,r0,lsl #2] bx lr align dlbl DCD |table_1| - ulbl - 8 ;Line 44 ENDP ;*** End embedded assembler *** EXPORT ||foo|| [CODE,DYNAMIC] IMPORT ||Lib$$Request$$armlib|| [CODE,WEAK] IMPORT table_1 [DATA,DYNAMIC] ATTR FILESCOPE ATTR SETVALUE Tag_ABI_PCS_wchar_t,4 ATTR SETVALUE Tag_ABI_enum_size,2 ATTR SETVALUE Tag_ABI_optimization_goals,2 ATTR SETSTRING Tag_conformance,"2.06" ATTR SETVALUE AV,18,1 ASSERT {ENDIAN} = "little" ASSERT {INTER} = {TRUE} ASSERT {ROPI} = {TRUE} ASSERT {RWPI} = {FALSE} ASSERT {IEEE_FULL} = {FALSE} ASSERT {IEEE_PART} = {FALSE} ASSERT {IEEE_JAVA} = {FALSE} END

As per my analysis,

For c-code - " armcc compiler is able to produce TEXTREL free code for table access by using RELOC"(see Line No:18,19 in above test.tmp.s file content)

For embedded assembly "" "assembler is not able to do the same......which results in TEXTREL's in code"...(see Line:44 "" where embedded assembler is not able to use RELOC)

So, I had manually added the RELOC 96, table_1 in embedded assembly, then TEXTREL's are not generated.

Is this the proper/recommended solution? Can I use the same for all tables?

Can you please explain what is the significance of 96 in "RELOC 96, table_1"?

Thanks In Advance,

satish
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Darisi V SATISH BABU over 12 years ago

Note: This was originally posted on 6th January 2011 at http://forums.arm.com

Hi Scott,

I need to use embedded assembly only. So, I had tested the sample code given by you and here are my observations:

The below mentioned PI version code is also generating TEXTREL's.....

__asm int foo_asm() { ldr r1, dlbl ulbl add r1, r1, pc ldr r0,[r1,r0,lsl #2] bx lr align dlbl dcd __cpp(table) - ulbl - 8 }

To analyze the behavior of arm compiler and embedded assembler, I had generated the test.tmp.s file from test.c file. I am unable to upload the files.There is error in uploading.So,i am copying the file contents:

test.c file content:
extern short int table_1[33]; int foo(int i) { return table_1[i]; } __asm int foo_asm(int i) { LDR r1, dlbl ulbl ADD r1, r1, pc LDR r0, [r1,r0,lsl #2] bx lr align dlbl DCD __cpp(table_1) - ulbl - 8 RELOC 96, table_1 //if this is used then only TEXTREL is not generated }

test.tmp.s file content - this is the .s file which is genrated by arm compiler for above code.
; generated by ARM NEON C/C++ Compiler, RVCT4.0 [Build 771] ; commandline armcc [--arm -c -S --gnu --no_hide_all --library_interface=aeabi_glibc -oobj/test.tmp.s --cpu=Cortex-A8 --fpu=VFPv3 --apcs=/interwork//fpic --no_unaligned_access -O3 -Otime --vectorize --enum_is_int --wchar32 obj/test.tmp.c] ARM REQUIRE8 PRESERVE8 AREA ||.text||, CODE, READONLY, ALIGN=2 ||foo|| PROC LDR r1,|L0.20| LDR r1,[pc,r1] ADD r0,r1,r0,LSL #1 LDRSH r0,[r0,#0] BX lr ENDP |L0.20| DCD 0x00000008 ;Line 18 RELOC 96, table_1 ;Line 19 AREA ||.arm_vfe_header||, DATA, READONLY, NOALLOC, ALIGN=2 DCD 0x00000000 ;*** Start embedded assembler *** #line 1 "obj/test.tmp.c" AREA ||.emb_text||, CODE, READONLY ARM EXPORT |foo_asm| [DYNAMIC] IMPORT |table_1| [DYNAMIC] #line 10 |foo_asm| PROC #line 11 LDR r1, dlbl ulbl ADD r1, r1, pc LDR r0, [r1,r0,lsl #2] bx lr align dlbl DCD |table_1| - ulbl - 8 ;Line 44 ENDP ;*** End embedded assembler *** EXPORT ||foo|| [CODE,DYNAMIC] IMPORT ||Lib$$Request$$armlib|| [CODE,WEAK] IMPORT table_1 [DATA,DYNAMIC] ATTR FILESCOPE ATTR SETVALUE Tag_ABI_PCS_wchar_t,4 ATTR SETVALUE Tag_ABI_enum_size,2 ATTR SETVALUE Tag_ABI_optimization_goals,2 ATTR SETSTRING Tag_conformance,"2.06" ATTR SETVALUE AV,18,1 ASSERT {ENDIAN} = "little" ASSERT {INTER} = {TRUE} ASSERT {ROPI} = {TRUE} ASSERT {RWPI} = {FALSE} ASSERT {IEEE_FULL} = {FALSE} ASSERT {IEEE_PART} = {FALSE} ASSERT {IEEE_JAVA} = {FALSE} END

As per my analysis,

For c-code - " armcc compiler is able to produce TEXTREL free code for table access by using RELOC"(see Line No:18,19 in above test.tmp.s file content)

For embedded assembly "" "assembler is not able to do the same......which results in TEXTREL's in code"...(see Line:44 "" where embedded assembler is not able to use RELOC)

So, I had manually added the RELOC 96, table_1 in embedded assembly, then TEXTREL's are not generated.

Is this the proper/recommended solution? Can I use the same for all tables?

Can you please explain what is the significance of 96 in "RELOC 96, table_1"?

Thanks In Advance,

satish
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