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Problem in generating position independent code with out TEXTREL

Darisi V SATISH BABU
Note: This was originally posted on 12th August 2010 at http://forums.arm.com

Hi Experts,

Issue:Not able to remove TEXTREL from our static library generated with --apcs /fpic option using armcc(RVCT 4.0 build 771  tool chain)

Description:
    We compiled our codebase(some modules with handwritten assembly) using armcc(RVCT 4.0 build 771  tool chain) to get static libraries, and then these are used by gstreamer module which further compiles using the above generated libraries with wrappers using GCC tool chain and creates shared objects(.so).

Even though we use equivalent --apcs /fpic compile time option during static library creation to remove position independent code, the TEXTREL are not going from library.
When we disable the (handwritten assembly) in the above mentioned codebase, TEXTRELs go away.
As there are lot of handwritten ARM assembly functions,its difficult to enable one by one and compile and check. :unsure:

So,Experts please throw some light on this issue.


Thanks In Advance,
satish
Parents
  • Arm Employee Badge
    Note: This was originally posted on 5th January 2011 at http://forums.arm.com

    The most maintainable solution would probably be to use C instead of embedded assembly.  If you're stuck using embedded assembly then manually changing/adding code is the only way to make it position independent.  The changes needed depends on what the non-PI code is doing, but usually involve adding the PC to some offset.  Here's a slightly improved/expanded example:

    In C:

    extern int table[] = { 1, 2, 3};
    int foo_c(int i) { return table[i]; }


    Here's a PI version in embedded asm (for ARM state):


    __asm int foo_asm() {
      ldr r1, dlbl
    ulbl
      add r1, r1, pc
      ldr r0,[r1,r0,lsl #2]
      bx lr
      align
    dlbl
      dcd __cpp(table) - ulbl - 8
    }


    'ulbl' is the labelling the position "using" ADD instruction.  'dlbl' is labelling the DCD. I think in Thumb state 'ulbl - 8' needs to be changed to 'ulbl -4'.

    The non-PI asm version would be:


    __asm int foo_asm_non_PI() {
      ldr r1, dlbl
      ldr r0,[r1,r0,lsl #2]
      bx lr
      align
    dlbl
      dcd __cpp(table)
    }


    Which is pretty much the same as:


    __asm int foo_asm_non_PI2() {
       ldr r1, =__cpp(table)
       ldr r0,[r1,r0,lsl #2]
       bx lr
    }
Reply
  • Arm Employee Badge
    Note: This was originally posted on 5th January 2011 at http://forums.arm.com

    The most maintainable solution would probably be to use C instead of embedded assembly.  If you're stuck using embedded assembly then manually changing/adding code is the only way to make it position independent.  The changes needed depends on what the non-PI code is doing, but usually involve adding the PC to some offset.  Here's a slightly improved/expanded example:

    In C:

    extern int table[] = { 1, 2, 3};
    int foo_c(int i) { return table[i]; }


    Here's a PI version in embedded asm (for ARM state):


    __asm int foo_asm() {
      ldr r1, dlbl
    ulbl
      add r1, r1, pc
      ldr r0,[r1,r0,lsl #2]
      bx lr
      align
    dlbl
      dcd __cpp(table) - ulbl - 8
    }


    'ulbl' is the labelling the position "using" ADD instruction.  'dlbl' is labelling the DCD. I think in Thumb state 'ulbl - 8' needs to be changed to 'ulbl -4'.

    The non-PI asm version would be:


    __asm int foo_asm_non_PI() {
      ldr r1, dlbl
      ldr r0,[r1,r0,lsl #2]
      bx lr
      align
    dlbl
      dcd __cpp(table)
    }


    Which is pretty much the same as:


    __asm int foo_asm_non_PI2() {
       ldr r1, =__cpp(table)
       ldr r0,[r1,r0,lsl #2]
       bx lr
    }
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