Hi,
Any suggestions for a cycle accurate simulator for Cortex-M devices other than Keil. We are currently using Keil uVision and came across some issues regarding the timing of a routine and would like to try another option.
What we are looking for is an instruction set simulator that can accurately report timing of the actual hardware.
Thanks,
HBL
Hi Bill,
Thanks for the product overview. The CPAK option sounds really interesting especially that we don't want to upgrade to DS-5 right now.
I do have a couple of questions on CPAK:
1. Would we be able to debug our application at the instruction level granularity with CPAK? What I mean is that we need to get a cycle-by-cycle view of what is going on in the processor.
2, Which ARM compiler is CPAK compatible with? We use GNU gcc (gcc-arm-none-eabi-4_9-2015q1-20150306).
HBL.
Hi Hanni, I think the CPAK sounds very well-suited for what you're looking to do. CPAKs execute in SoCDesigner which means that you can take advantage of all of SoCDesigner's debug and analysis capabilities. This means that we offer source level debugging via our interface to RVDS/DS-5 or you can alternatively use the built-in disassembler which comes with the tool. The analysis capabilities of SoCDesigner let you view what is going on in both the software and hardware on a per-cycle basis. You can even synchronize the analysis window to see the exact number of cycles from when a software line executes and any event in hardware.
The ARM processor models which run in our CPAKs run un-modified ARM binaries so compiler versions aren't a problem. If you're running your application today on any other ISS model then it should have no problems running on our CPAKs.
We would be happy to set up a demonstration of any of our CPAKs and walk you through all that we can do. Please feel free to contact me directly and I can set that up. My email is bill@carbondesignsystems.com. We can of course just continue to exchange information here as well however if you would prefer that.