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ARM926 Interrupt exception

rmelizalde rmelizalde
Note: This was originally posted on 27th August 2009 at http://forums.arm.com

Hi,

I would like to program an interrupt handler for ARM926ej.

According to reference, when CPU is interrupted, it jumps to address 0xFFFF0018 (interrupt vector).

Then, I suppose I have to program a jump instruction to my handler in that address. But I don't know how.

I'm using GNU toolchain.

Thank you very much
Ricardo
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  • Note: This was originally posted on 10th September 2009 at http://forums.arm.com

    Thx Rob,

    Our ARM926ej leaves exception jump adress in High Mem. That is 0xFFFF0018 for Interrupt Exception.

    Then, I copy "by hand" code written in .text section "LDR pc, isr_handler_Addr" to 0xFFFF0018 with load and store instructions.

    Then I enable and unmask my interrupt source, I expect the CPU to jump to 0xFFFF0018 when interrupted but instead it jumps to 0xFFFF0004 (INSTRUCTION NOT DEFINED) and therefore dies.

    Thanks,
    Ricardo

    Normally, meaning most cases interrupts are at the lowest (physical) memory addresses so the Reset vector is at 0x00000000 followed by the other vectors at 0x4, 0x8, etc... It is possible to use a signal which will move the interrupt vector locations to high memory as is apparently done with your design.

    There is excellent documentation on the ARM Web-site if you go to Technical Support and search. I am not sure if there examples are copyrighted or if they can be used on this forum. ARM gives the example of using addresses from a Literal pool with the LDR instruction or Load Register instruction.

    LDR pc, Reset_Addr   ; jump to reset ISR

    I will point you to this invaluable code. See Example 6.1 in Section 6.2.2 under Realview Software Development Tools in the Documentation section. You need to learn to search and read some.
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  • Note: This was originally posted on 10th September 2009 at http://forums.arm.com

    Thx Rob,

    Our ARM926ej leaves exception jump adress in High Mem. That is 0xFFFF0018 for Interrupt Exception.

    Then, I copy "by hand" code written in .text section "LDR pc, isr_handler_Addr" to 0xFFFF0018 with load and store instructions.

    Then I enable and unmask my interrupt source, I expect the CPU to jump to 0xFFFF0018 when interrupted but instead it jumps to 0xFFFF0004 (INSTRUCTION NOT DEFINED) and therefore dies.

    Thanks,
    Ricardo

    Normally, meaning most cases interrupts are at the lowest (physical) memory addresses so the Reset vector is at 0x00000000 followed by the other vectors at 0x4, 0x8, etc... It is possible to use a signal which will move the interrupt vector locations to high memory as is apparently done with your design.

    There is excellent documentation on the ARM Web-site if you go to Technical Support and search. I am not sure if there examples are copyrighted or if they can be used on this forum. ARM gives the example of using addresses from a Literal pool with the LDR instruction or Load Register instruction.

    LDR pc, Reset_Addr   ; jump to reset ISR

    I will point you to this invaluable code. See Example 6.1 in Section 6.2.2 under Realview Software Development Tools in the Documentation section. You need to learn to search and read some.
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