• Locked Locked
  • Replies 4 replies
  • Subscribers 119 subscribers
  • Views 4427 views
  • Users 0 members are here
Options
Related
How was your experience today?
This discussion has been locked.
You can no longer post new replies to this discussion. If you have a question you can start a new discussion

Setting up uvision4 debugger with Cortex-M1 on Altera Cyclone III

Siew Kei Lam
Note: This was originally posted on 21st June 2011 at http://forums.arm.com

I am trying to setup the uvision4 debugger to communicate with Cortex M1 on Altera Cyclone III through the USB JTAG interface. I have observed from the Cortex-M1 development kit that this can be done by instantiating the Virtual JTAG megafunction and implementing a glue logic to interface the Virtual JTAG with the Cortex-M1 RTL. Unfortunately, the Verilog description of the glue logic is not visible.

Can anyone give me some pointers on how to go about designing the glue logic between Virtual JTAG and Cortex-M1? Or is there another alternative to this? Thanks.
Parents
  • Arm Employee Badge
    Note: This was originally posted on 23rd June 2011 at http://forums.arm.com

    I have discussed with the engineer who worked on this. When Cortex-M1 was developed, the Virtual JTAG detail specification was not open to public. As a result, we were unable to include the glue logic to the Cortex-M1 RTL package.

    You should be able to bring out the JTAG/Serial Wire signals to the FPGA top level (you need to add a tristate buffer to SWIO), then you should be able to connect it to the debugger using Keil ULINK, Segger J-Link or other debuggers, using this separated JTAG interface.

    Alternatively you can contact our support team to see if we can provide the detail of this glue logic to you.
Reply
  • Arm Employee Badge
    Note: This was originally posted on 23rd June 2011 at http://forums.arm.com

    I have discussed with the engineer who worked on this. When Cortex-M1 was developed, the Virtual JTAG detail specification was not open to public. As a result, we were unable to include the glue logic to the Cortex-M1 RTL package.

    You should be able to bring out the JTAG/Serial Wire signals to the FPGA top level (you need to add a tristate buffer to SWIO), then you should be able to connect it to the debugger using Keil ULINK, Segger J-Link or other debuggers, using this separated JTAG interface.

    Alternatively you can contact our support team to see if we can provide the detail of this glue logic to you.
Children
No data