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Why Cache L1 Counters disable on Streamline

Olfat

Hello every one,

ARM DS-5 (University) streamline to read counter events from Beagle Bone Black board. for some reason i can not get the l1Caches counter to work. Any Advice?

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Thanks

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    Only a limited number of the Cortex-A8 counters can be selected at the same time. In the black bar that says Cortex-A8, it says 0 of 4 are available to be selected. This is because 4 counters (plus Clock: Cycles) are already selected under Events to Collect. If you remove one of the events there (Branch: Mispredicted, Cache: L2 access, Cache: L2 miss or Instructions: Executed) you will be able to select a different counter.

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  • 0

    Only a limited number of the Cortex-A8 counters can be selected at the same time. In the black bar that says Cortex-A8, it says 0 of 4 are available to be selected. This is because 4 counters (plus Clock: Cycles) are already selected under Events to Collect. If you remove one of the events there (Branch: Mispredicted, Cache: L2 access, Cache: L2 miss or Instructions: Executed) you will be able to select a different counter.

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