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Does DS-5 ultimate evaluation version offer an FVP to ARMv8 executable?

I have compiled a simple "Hello World" program on DS-5 ultimate evaluation version and couldn't find a bare metal FVP on which I can run it. When I select "ARM FVP->VE_AEMv8x1->Bare Metal Debug->Debug ARMAEMv8-A" in "Connection" tab of "Debug Configuration" connection fails and I see a message that "Unable to connect to armv8_FVP"

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  • Yes, there is an ARMv8-A model provided with DS-5 Ultimate edition.  It's the "VE_AEMv8x4" (4 cores, based on Versatile Express memory map):

      ARM FVP --> VE_AEMv8x4 --> Bare Metal Debug --> Debug ARMAEMv8-A_MP_<n>

    Where n is 0 to 3.

    As this is a multi-core target, if you are writing bare metal code you will need to take this into account.  This could be as simple as putting the cores you do not want to use into stand-by.  Alternatively, having a proper multi-core boot scheme (DS-5 comes with an example).

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  • Yes, there is an ARMv8-A model provided with DS-5 Ultimate edition.  It's the "VE_AEMv8x4" (4 cores, based on Versatile Express memory map):

      ARM FVP --> VE_AEMv8x4 --> Bare Metal Debug --> Debug ARMAEMv8-A_MP_<n>

    Where n is 0 to 3.

    As this is a multi-core target, if you are writing bare metal code you will need to take this into account.  This could be as simple as putting the cores you do not want to use into stand-by.  Alternatively, having a proper multi-core boot scheme (DS-5 comes with an example).

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  • On selecting ARM FVP --> VE_AEMv8x4 --> Bare Metal Debug --> Debug ARMAEMv8-A_MP_<0> I am getting following error

    "ERROR(TAB180): The semihosting breakpoint address has not been specified"

    How could I resolve this error?

    How could I put other core into stand-by?

    Best Regards,

  • I've not noticed that before, but I get it when connecting to the FVP as well.  Doesn't seem to stop semihosting from working, my test image (which had a number of semihosting calls) worked without a hitch.  Have you tried building and running one of the example projects?

    On the putting the cores into stand-by, there are a couple of ways you could do this.  A relatively simple method would be to have a check at the beginning of your initialization code.  Something like this:

      MRS x0, MPIDR_EL1   ; Read MPDIR, which reports affinity
      AND x0, x0, #0xFF   ; Mask to leave Aff0 field
      CBZ x0, boot        ; If Aff0==0 (core 0), branch to boot code
    sleep
      WFI                 ; If Aff0!=0 (cores 1 to 3), go to sleep
      B sleep
    boot