Difference between SWI and SVC

As you're actually calling an interrupt, the standard interrupt latency applies here.

Eg. at least 12 clock cycles (16 or 15 on Cortex-M0/Cortex-M0+).

That means when you issue SVC #imm, the SVC_Handler is executed "immediately" (well, a higher priority interrupt could in fact precede the SVC_Handler interrupt service routine, increasing the latency to 'anything').

I'd like to point you to A Beginner’s Guide on Interrupt Latency, in case you haven't seen it; it is an excellent document that covers all this; it also gives you insight in some of the internal workings of the processor, which is very good to have in mind while writing time critical code.

PS: Please mark daith's answer correct.

As you're actually calling an interrupt, the standard interrupt latency applies here.

Eg. at least 12 clock cycles (16 or 15 on Cortex-M0/Cortex-M0+).

That means when you issue SVC #imm, the SVC_Handler is executed "immediately" (well, a higher priority interrupt could in fact precede the SVC_Handler interrupt service routine, increasing the latency to 'anything').

I'd like to point you to A Beginner’s Guide on Interrupt Latency, in case you haven't seen it; it is an excellent document that covers all this; it also gives you insight in some of the internal workings of the processor, which is very good to have in mind while writing time critical code.

PS: Please mark daith's answer correct.