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Cortex A8 preload engine (PLE) error

Ted Middleton
Note: This was originally posted on 24th November 2011 at http://forums.arm.com

I have a user-mode Linux application running on a Cortex-A8 (a TI 8148 Davinci chip). I have a shared memory region that I'm using to communicate data back and forth between the ARM core and the TI c674x DSP. The shared memory region is a ring buffer made of 32k segments (the size of the 8148's L2 cache ways). I've locked down 3 of the L2 cache ways and I'm trying to use the L2 PLE (preload engine) - the L2 feature accessed through coprocessor 15 c11 - to asynchronously preload and writeback the ring buffer segments. The ring buffer itself is located in physically and virtually contiguous memory - we're using TI's cmem module to allocate out of a memory hole. Moreover, I've checked the linux struct page flags for the ring buffer pages and they seem to all be uniform and fairly kosher. Plain-vanilla loads and stores from the ring buffer work just fine, as do coprocessor 15 based cache writeback operations (performed in privileged mode, of course).

Anyways, everything goes quite nicely for a while (anywhere from 3 to 10 PLE transfers complete successfully), until a PLE transfer errors-out at a page boundary. It's a different page boundary (both virtual and physical address) each time, and it's a different number of ring buffer segments and a different number of pages into the ring buffer segment each time this happens. The error itself, from table 3-132 in the ARM Cortex-A8 Technical Reference Manual, is "b1000101", or "translation fault, section".

Does anyone know what this error means? At first I thought that maybe it was because the page was marked as uncached, but looking at the page properties (with /proc/kpageflags), that doesn't seem to be the case.

Edit: One more detail - this failure only happens with preload operations - not writebacks. Or at least I haven't seen it happen with a writeback yet.
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  • Arm Employee Badge
    Note: This was originally posted on 25th November 2011 at http://forums.arm.com

    [font=Arial]
    I'm wondering if maybe Linux is switching to another process which coincidentally DOES have that same VA mapped, and my L2 cache data is getting written out to the wrong place (ie a page in that other process)?

    Yes, corruption would certainly result if the VA->PA translation changed to something else and the PLE was still running.

    What's supposed to prevent this from happening?


    Is suspect the answer is "software" =)

    I'm not a PLE expert, but AFAICT the PLE uses the same page tables as currently mapped on the core, so if the OS context switches from one process to another you either have to (1) stall the context switch waiting for the pending PLE reqeusts to complete, or (2) cancel pending PLE requests, [/font](3) "pause" the transfer, switch the process out, and "resume" when it gets switched back in again.

    Cheers,
    Iso
Reply
  • Arm Employee Badge
    Note: This was originally posted on 25th November 2011 at http://forums.arm.com

    [font=Arial]
    I'm wondering if maybe Linux is switching to another process which coincidentally DOES have that same VA mapped, and my L2 cache data is getting written out to the wrong place (ie a page in that other process)?

    Yes, corruption would certainly result if the VA->PA translation changed to something else and the PLE was still running.

    What's supposed to prevent this from happening?


    Is suspect the answer is "software" =)

    I'm not a PLE expert, but AFAICT the PLE uses the same page tables as currently mapped on the core, so if the OS context switches from one process to another you either have to (1) stall the context switch waiting for the pending PLE reqeusts to complete, or (2) cancel pending PLE requests, [/font](3) "pause" the transfer, switch the process out, and "resume" when it gets switched back in again.

    Cheers,
    Iso
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