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MMU with 16MB super sections - howto?

Ramesh Shanmugasundaram
Note: This was originally posted on 11th July 2011 at http://forums.arm.com

Hi,

I am trying to setup MMU with 1:1 scheme (VA=PA). I wanted to try with a 16MB super section.

I first tried with 1MB section and created a 1:1 TLB with each entry being 1MB and it takes 16KB space with 4K entries. This works

Then i tried with 16MB super sections with only difference being - bit 18 set for each entry in the TLB. This is as per the ARM TRM.

Basically i am trying this during boot and hence i don't have 16KB free space to have 1MB TLB entry size. So i thought a 16MB entry will result in 256 entries => 1K space.

I am using ARM1176ej-s processor. When i searched i get this link "http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0360e/CBACHHJG.html"

" Because each first level page table entry covers a 1MB region of virtual memory, the 16MB supersections require that 16 identical copies of the first level descriptor of the supersection exist in the first level page table."

I don't understand this line. Is the first level page table is always meant to be 16KB size? What is the benefit of 16MB super section then?

Can anyone post and example of having a 16MB supersection in TLB (256 entries) with 1:1 scheme?

Thanks.
Parents
  • Note: This was originally posted on 8th February 2013 at http://forums.arm.com

      Hi,

    I am trying to setup MMU using super section, too. I think the different things super section and section is just bit 18 set or not in the L1 page table. In my case,[size="2"] [size="2"][size="2"]the section page table [/size][/size][/size][size="2"][size="2"][size="2"][size="2"][size="2"]is wo[size="2"]rking [/size] [/size][/size][/size][/size][/size]when the MMU enable. However,  [size="2"][size="2"]it is not working when [size="2"]I set the [/size][/size][/size][size="2"][size="2"][size="2"][size="2"][size="2"][size="2"][size="2"][size="2"]bit 18[size="2"] [size="2"]into [/size][/size][/size][/size][/size][/size][/size][/size][/size][/size]the same page table[size="2"]. Sure, [size="2"]I [size="2"]am [size="2"]clear set [size="2"][size="2"]the base address and ot[size="2"]her[size="2"] [size="2"]attri[size="2"]butes in th[size="2"]e L1 [size="2"]page table[/size].[/size][/size][/size][/size][/size][/size][/size][/size][/size][/size]

    What is the problem? Is the super section able to [size="2"]enable[/size] paging?
    [/size]   
Reply
  • Note: This was originally posted on 8th February 2013 at http://forums.arm.com

      Hi,

    I am trying to setup MMU using super section, too. I think the different things super section and section is just bit 18 set or not in the L1 page table. In my case,[size="2"] [size="2"][size="2"]the section page table [/size][/size][/size][size="2"][size="2"][size="2"][size="2"][size="2"]is wo[size="2"]rking [/size] [/size][/size][/size][/size][/size]when the MMU enable. However,  [size="2"][size="2"]it is not working when [size="2"]I set the [/size][/size][/size][size="2"][size="2"][size="2"][size="2"][size="2"][size="2"][size="2"][size="2"]bit 18[size="2"] [size="2"]into [/size][/size][/size][/size][/size][/size][/size][/size][/size][/size]the same page table[size="2"]. Sure, [size="2"]I [size="2"]am [size="2"]clear set [size="2"][size="2"]the base address and ot[size="2"]her[size="2"] [size="2"]attri[size="2"]butes in th[size="2"]e L1 [size="2"]page table[/size].[/size][/size][/size][/size][/size][/size][/size][/size][/size][/size]

    What is the problem? Is the super section able to [size="2"]enable[/size] paging?
    [/size]   
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