Hello everyone, I'm analysing u-boot for s3c2440(arm920t), and at the first stage u-boot does something like this:
mov R0, #0 mcr P15, 0, R0, C7, C7, 0 ; flush v3/v4 caches mcr P15, 0, R0, C8, C7, 0 ; flush v4 TLB mrc P15, 0, R0, C1, C0, 0 bic R0, R0, #0x00000087 ; clear bits 7, 2:0, disable MMU, D-cache, Data Address Alignement ... mcr P15, 0, R0, C1, C0, 0
mov R0, #0
mcr P15, 0, R0, C7, C7, 0 ; flush v3/v4 caches
mcr P15, 0, R0, C8, C7, 0 ; flush v4 TLB
mrc P15, 0, R0, C1, C0, 0
bic R0, R0, #0x00000087 ; clear bits 7, 2:0, disable MMU, D-cache, Data Address Alignement
...
mcr P15, 0, R0, C1, C0, 0
what's the difference between flush and disable cache? And v3/v4 caches mean what? Thank you in advance for any information.
> what's the difference between flush and disable cache?
A flush ensures that any dirty data in the cache is written out to main memory. Disable turns them off so they are no longer used for subsequent memory accesses.
> And v3/v4 caches mean what?
Not a clue - might be worth asking the u-boot maintainers =)
HTH,
Pete
thank you Pete. So you mean we need to save the content in cache? But the bootloader is initialising the hardware, there may not be anything important in the cache. Also we havenot define to which part of memory to receive the cache content. weird?
> But the bootloader is initialising the hardware, there may not be anything important in the cache.
U-boot is rarely the first level of boot in an ARM system - there is usually some form of ROM-based bootloader which runs first and sets up DDR controllers, flash controllers, etc. In many systems this may enable caches to accelerate the boot process.
If caches are not enabled, then the steps u-boot takes to "disable them" are benign and do nothing.