Hello everyone, I'm analysing u-boot for s3c2440(arm920t), and at the first stage u-boot does something like this:
mov R0, #0 mcr P15, 0, R0, C7, C7, 0 ; flush v3/v4 caches mcr P15, 0, R0, C8, C7, 0 ; flush v4 TLB mrc P15, 0, R0, C1, C0, 0 bic R0, R0, #0x00000087 ; clear bits 7, 2:0, disable MMU, D-cache, Data Address Alignement ... mcr P15, 0, R0, C1, C0, 0
mov R0, #0
mcr P15, 0, R0, C7, C7, 0 ; flush v3/v4 caches
mcr P15, 0, R0, C8, C7, 0 ; flush v4 TLB
mrc P15, 0, R0, C1, C0, 0
bic R0, R0, #0x00000087 ; clear bits 7, 2:0, disable MMU, D-cache, Data Address Alignement
...
mcr P15, 0, R0, C1, C0, 0
what's the difference between flush and disable cache? And v3/v4 caches mean what? Thank you in advance for any information.