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DS-5 Arm Streamline: What Exactly "Cycles" Is

Xiaowan Dong

Hi Everyone,

I have a question regarding the "cycles" item in arm streamline analysis report. According to the annotation, it is "the number of core clock cycles". Does it mean it is non-halting cycles instead of total cycles?

Thank you!

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    Clock Cycles in Streamline comes from the PMCCNTR (Performance Monitor Cycle Count) register. It does not include clock cycles when the processor is in a sleep state like WFI (Wait For Interrupt) and not executing any instructions. I assume this is what you mean when you refer to halting cycles. If you have access, the ARM Architecture Reference Manual for ARMv7-A has all the details.

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    Clock Cycles in Streamline comes from the PMCCNTR (Performance Monitor Cycle Count) register. It does not include clock cycles when the processor is in a sleep state like WFI (Wait For Interrupt) and not executing any instructions. I assume this is what you mean when you refer to halting cycles. If you have access, the ARM Architecture Reference Manual for ARMv7-A has all the details.

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